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Commit a2817485 authored by Tao Zhang's avatar Tao Zhang
Browse files

ARM: dts: msm: Add apss dl cti0 for shima 

Add app dl cti0 to device tree for DCC LLCC timeout on shima.

Change-Id: I8f8bd5626a848c015631849b1790e18582109c22
parent 2e58ae20

qcom/shima-coresight.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -3598,6 +3598,18 @@ 
		clock-names = "apb_pclk";

	};



	cti0_apss_dl: cti@7862000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x000bb966>;

		reg = <0x7862000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-apss_dl_cti0";



		clocks = <&aopcc QDSS_CLK>;

		clock-names = "apb_pclk";

	};



	snoc: snoc {

		compatible = "qcom,coresight-dummy";

		coresight-name = "coresight-snoc";