Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next

*******************************************************************************/

/*

 * 80003ES2LAN Gigabit Ethernet Controller (Copper)

/* 80003ES2LAN Gigabit Ethernet Controller (Copper)

 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)

 */

							   1 = 50-80M

							   2 = 80-110M

							   3 = 110-140M

							   4 = >140M */

							   4 = >140M

							*/

/* Kumeran Mode Control Register (Page 193, Register 16) */

#define GG82563_KMCR_PASS_FALSE_CARRIER		 0x0800

/* In-Band Control Register (Page 194, Register 18) */

#define GG82563_ICR_DIS_PADDING			 0x0010 /* Disable Padding */

/*

 * A table for the GG82563 cable length where the range is defined

/* A table for the GG82563 cable length where the range is defined

 * with a lower bound at "index" and the upper bound at

 * "index + 5".

 */

	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>

			  E1000_EECD_SIZE_EX_SHIFT);

	/*

	 * Added to a constant, "size" becomes the left-shift value

	/* Added to a constant, "size" becomes the left-shift value

	 * for setting word_size.

	 */

	size += NVM_WORD_SIZE_BASE_SHIFT;

		if (!(swfw_sync & (fwmask | swmask)))

			break;

		/*

		 * Firmware currently using resource (fwmask)

		/* Firmware currently using resource (fwmask)

		 * or other software thread using resource (swmask)

		 */

		e1000e_put_hw_semaphore(hw);

	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {

		page_select = GG82563_PHY_PAGE_SELECT;

	} else {

		/*

		 * Use Alternative Page Select register to access

		/* Use Alternative Page Select register to access

		 * registers 30 and 31

		 */

		page_select = GG82563_PHY_PAGE_SELECT_ALT;

	}

	if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {

		/*

		 * The "ready" bit in the MDIC register may be incorrectly set

		/* The "ready" bit in the MDIC register may be incorrectly set

		 * before the device has completed the "Page Select" MDI

		 * transaction.  So we wait 200us after each MDI command...

		 */

	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {

		page_select = GG82563_PHY_PAGE_SELECT;

	} else {

		/*

		 * Use Alternative Page Select register to access

		/* Use Alternative Page Select register to access

		 * registers 30 and 31

		 */

		page_select = GG82563_PHY_PAGE_SELECT_ALT;

	}

	if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {

		/*

		 * The "ready" bit in the MDIC register may be incorrectly set

		/* The "ready" bit in the MDIC register may be incorrectly set

		 * before the device has completed the "Page Select" MDI

		 * transaction.  So we wait 200us after each MDI command...

		 */

	u16 phy_data;

	bool link;

	/*

	 * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI

	/* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI

	 * forced whenever speed and duplex are forced.

	 */

	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);

			return ret_val;

		if (!link) {

			/*

			 * We didn't get link.

			/* We didn't get link.

			 * Reset the DSP and cross our fingers.

			 */

			ret_val = e1000e_phy_reset_dsp(hw);

	if (ret_val)

		return ret_val;

	/*

	 * Resetting the phy means we need to verify the TX_CLK corresponds

	/* Resetting the phy means we need to verify the TX_CLK corresponds

	 * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.

	 */

	phy_data &= ~GG82563_MSCR_TX_CLK_MASK;

	else

		phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;

	/*

	 * In addition, we must re-enable CRS on Tx for both half and full

	/* In addition, we must re-enable CRS on Tx for both half and full

	 * duplex.

	 */

	phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;

	s32 ret_val;

	u16 kum_reg_data;

	/*

	 * Prevent the PCI-E bus from sticking if there is no TLP connection

	/* Prevent the PCI-E bus from sticking if there is no TLP connection

	 * on the last TLP read/write transaction when MAC is reset.

	 */

	ret_val = e1000e_disable_pcie_master(hw);

			hw->dev_spec.e80003es2lan.mdic_wa_enable = false;

	}

	/*

	 * Clear all of the statistics registers (clear on read).  It is

	/* Clear all of the statistics registers (clear on read).  It is

	 * important that we do this after we have tried to establish link

	 * because the symbol error count will increment wildly if there

	 * is no link.

		reg |= (1 << 28);

	ew32(TARC(1), reg);

	/*

	 * Disable IPv6 extension header parsing because some malformed

	/* Disable IPv6 extension header parsing because some malformed

	 * IPv6 headers can hang the Rx.

	 */

	reg = er32(RFCTL);

	if (ret_val)

		return ret_val;

	/*

	 * Options:

	/* Options:

	 *   MDI/MDI-X = 0 (default)

	 *   0 - Auto for all speeds

	 *   1 - MDI mode

		break;

	}

	/*

	 * Options:

	/* Options:

	 *   disable_polarity_correction = 0 (default)

	 *       Automatic Correction for Reversed Cable Polarity

	 *   0 - Disabled

	if (ret_val)

		return ret_val;

	/*

	 * Do not init these registers when the HW is in IAMT mode, since the

	/* Do not init these registers when the HW is in IAMT mode, since the

	 * firmware will have already initialized them.  We only initialize

	 * them if the HW is not in IAMT mode.

	 */

			return ret_val;

	}

	/*

	 * Workaround: Disable padding in Kumeran interface in the MAC

	/* Workaround: Disable padding in Kumeran interface in the MAC

	 * and in the PHY to avoid CRC errors.

	 */

	ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);

	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

	ew32(CTRL, ctrl);

	/*

	 * Set the mac to wait the maximum time between each

	/* Set the mac to wait the maximum time between each

	 * iteration and increase the max iterations when

	 * polling the phy; this fixes erroneous timeouts at 10Mbps.

	 */

{

	s32 ret_val = 0;

	/*

	 * If there's an alternate MAC address place it in RAR0

	/* If there's an alternate MAC address place it in RAR0

	 * so that it will override the Si installed default perm

	 * address.

	 */

*******************************************************************************/

/*

 * 82571EB Gigabit Ethernet Controller

/* 82571EB Gigabit Ethernet Controller

 * 82571EB Gigabit Ethernet Controller (Copper)

 * 82571EB Gigabit Ethernet Controller (Fiber)

 * 82571EB Dual Port Gigabit Mezzanine Adapter

		if (((eecd >> 15) & 0x3) == 0x3) {

			nvm->type = e1000_nvm_flash_hw;

			nvm->word_size = 2048;

			/*

			 * Autonomous Flash update bit must be cleared due

			/* Autonomous Flash update bit must be cleared due

			 * to Flash update issue.

			 */

			eecd &= ~E1000_EECD_AUPDEN;

		nvm->type = e1000_nvm_eeprom_spi;

		size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>

				  E1000_EECD_SIZE_EX_SHIFT);

		/*

		 * Added to a constant, "size" becomes the left-shift value

		/* Added to a constant, "size" becomes the left-shift value

		 * for setting word_size.

		 */

		size += NVM_WORD_SIZE_BASE_SHIFT;

		/* FWSM register */

		mac->has_fwsm = true;

		/*

		 * ARC supported; valid only if manageability features are

		/* ARC supported; valid only if manageability features are

		 * enabled.

		 */

		mac->arc_subsystem_valid = !!(er32(FWSM) &

		break;

	}

	/*

	 * Ensure that the inter-port SWSM.SMBI lock bit is clear before

	/* Ensure that the inter-port SWSM.SMBI lock bit is clear before

	 * first NVM or PHY access. This should be done for single-port

	 * devices, and for one port only on dual-port devices so that

	 * for those devices we can still use the SMBI lock to synchronize

		ew32(SWSM, swsm & ~E1000_SWSM_SMBI);

	}

	/*

	 * Initialize device specific counter of SMBI acquisition

	 * timeouts.

	 */

	/* Initialize device specific counter of SMBI acquisition timeouts. */

	hw->dev_spec.e82571.smb_counter = 0;

	return 0;

	switch (hw->mac.type) {

	case e1000_82571:

	case e1000_82572:

		/*

		 * The 82571 firmware may still be configuring the PHY.

		/* The 82571 firmware may still be configuring the PHY.

		 * In this case, we cannot access the PHY until the

		 * configuration is done.  So we explicitly set the

		 * PHY ID.

	s32 fw_timeout = hw->nvm.word_size + 1;

	s32 i = 0;

	/*

	 * If we have timedout 3 times on trying to acquire

	/* If we have timedout 3 times on trying to acquire

	 * the inter-port SMBI semaphore, there is old code

	 * operating on the other port, and it is not

	 * releasing SMBI. Modify the number of times that

	if (ret_val)

		return ret_val;

	/*

	 * If our nvm is an EEPROM, then we're done

	/* If our nvm is an EEPROM, then we're done

	 * otherwise, commit the checksum to the flash NVM.

	 */

	if (hw->nvm.type != e1000_nvm_flash_hw)

	/* Reset the firmware if using STM opcode. */

	if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {

		/*

		 * The enabling of and the actual reset must be done

		/* The enabling of and the actual reset must be done

		 * in two write cycles.

		 */

		ew32(HICR, E1000_HICR_FW_RESET_ENABLE);

	u32 i, eewr = 0;

	s32 ret_val = 0;

	/*

	 * A check for invalid values:  offset too large, too many words,

	/* A check for invalid values:  offset too large, too many words,

	 * and not enough words.

	 */

	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||

	} else {

		data &= ~IGP02E1000_PM_D0_LPLU;

		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);

		/*

		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used

		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used

		 * during Dx states where the power conservation is most

		 * important.  During driver activity we should enable

		 * SmartSpeed, so performance is maintained.

	u32 ctrl, ctrl_ext, eecd, tctl;

	s32 ret_val;

	/*

	 * Prevent the PCI-E bus from sticking if there is no TLP connection

	/* Prevent the PCI-E bus from sticking if there is no TLP connection

	 * on the last TLP read/write transaction when MAC is reset.

	 */

	ret_val = e1000e_disable_pcie_master(hw);

	usleep_range(10000, 20000);

	/*

	 * Must acquire the MDIO ownership before MAC reset.

	/* Must acquire the MDIO ownership before MAC reset.

	 * Ownership defaults to firmware after a reset.

	 */

	switch (hw->mac.type) {

		/* We don't want to continue accessing MAC registers. */

		return ret_val;

	/*

	 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.

	/* Phy configuration from NVM just starts after EECD_AUTO_RD is set.

	 * Need to wait for Phy configuration completion before accessing

	 * NVM and Phy.

	 */

	switch (hw->mac.type) {

	case e1000_82571:

	case e1000_82572:

		/*

		 * REQ and GNT bits need to be cleared when using AUTO_RD

		/* REQ and GNT bits need to be cleared when using AUTO_RD

		 * to access the EEPROM.

		 */

		eecd = er32(EECD);

	e_dbg("Initializing the IEEE VLAN\n");

	mac->ops.clear_vfta(hw);

	/* Setup the receive address. */

	/*

	/* Setup the receive address.

	 * If, however, a locally administered address was assigned to the

	 * 82571, we must reserve a RAR for it to work around an issue where

	 * resetting one port will reload the MAC on the other port.

		break;

	}

	/*

	 * Clear all of the statistics registers (clear on read).  It is

	/* Clear all of the statistics registers (clear on read).  It is

	 * important that we do this after we have tried to establish link

	 * because the symbol error count will increment wildly if there

	 * is no link.

		ew32(PBA_ECC, reg);

	}

	/*

	 * Workaround for hardware errata.

	/* Workaround for hardware errata.

	 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572

	 */

	if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) {

		ew32(CTRL_EXT, reg);

	}

	/*

	 * Disable IPv6 extension header parsing because some malformed

	/* Disable IPv6 extension header parsing because some malformed

	 * IPv6 headers can hang the Rx.

	 */

	if (hw->mac.type <= e1000_82573) {

		reg |= (1 << 22);

		ew32(GCR, reg);

		/*

		 * Workaround for hardware errata.

		/* Workaround for hardware errata.

		 * apply workaround for hardware errata documented in errata

		 * docs Fixes issue where some error prone or unreliable PCIe

		 * completions are occurring, particularly with ASPM enabled.

	case e1000_82574:

	case e1000_82583:

		if (hw->mng_cookie.vlan_id != 0) {

			/*

			 * The VFTA is a 4096b bit-field, each identifying

			/* The VFTA is a 4096b bit-field, each identifying

			 * a single VLAN ID.  The following operations

			 * determine which 32b entry (i.e. offset) into the

			 * array we want to set the VLAN ID (i.e. bit) of

		break;

	}

	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {

		/*

		 * If the offset we want to clear is the same offset of the

		/* If the offset we want to clear is the same offset of the

		 * manageability VLAN ID, then clear all bits except that of

		 * the manageability unit.

		 */

	ctrl = hw->mac.ledctl_mode2;

	if (!(E1000_STATUS_LU & er32(STATUS))) {

		/*

		 * If no link, then turn LED on by setting the invert bit

		/* If no link, then turn LED on by setting the invert bit

		 * for each LED that's "on" (0x0E) in ledctl_mode2.

		 */

		for (i = 0; i < 4; i++)

	u16 receive_errors = 0;

	s32 ret_val = 0;

	/*

	 * Read PHY Receive Error counter first, if its is max - all F's then

	/* Read PHY Receive Error counter first, if its is max - all F's then

	 * read the Base1000T status register If both are max then PHY is hung.

	 */

	ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);

 **/

static s32 e1000_setup_link_82571(struct e1000_hw *hw)

{

	/*

	 * 82573 does not have a word in the NVM to determine

	/* 82573 does not have a word in the NVM to determine

	 * the default flow control setting, so we explicitly

	 * set it to full.

	 */

	switch (hw->mac.type) {

	case e1000_82571:

	case e1000_82572:

		/*

		 * If SerDes loopback mode is entered, there is no form

		/* If SerDes loopback mode is entered, there is no form

		 * of reset to take the adapter out of that mode.  So we

		 * have to explicitly take the adapter out of loopback

		 * mode.  This prevents drivers from twiddling their thumbs

		switch (mac->serdes_link_state) {

		case e1000_serdes_link_autoneg_complete:

			if (!(status & E1000_STATUS_LU)) {

				/*

				 * We have lost link, retry autoneg before

				/* We have lost link, retry autoneg before

				 * reporting link failure

				 */

				mac->serdes_link_state =

			break;

		case e1000_serdes_link_forced_up:

			/*

			 * If we are receiving /C/ ordered sets, re-enable

			/* If we are receiving /C/ ordered sets, re-enable

			 * auto-negotiation in the TXCW register and disable

			 * forced link in the Device Control register in an

			 * attempt to auto-negotiate with our link partner.

		case e1000_serdes_link_autoneg_progress:

			if (rxcw & E1000_RXCW_C) {

				/*

				 * We received /C/ ordered sets, meaning the

				/* We received /C/ ordered sets, meaning the

				 * link partner has autonegotiated, and we can

				 * trust the Link Up (LU) status bit.

				 */

					e_dbg("AN_PROG   -> DOWN\n");

				}

			} else {

				/*

				 * The link partner did not autoneg.

				/* The link partner did not autoneg.

				 * Force link up and full duplex, and change

				 * state to forced.

				 */

		case e1000_serdes_link_down:

		default:

			/*

			 * The link was down but the receiver has now gained

			/* The link was down but the receiver has now gained

			 * valid sync, so lets see if we can bring the link

			 * up.

			 */

			mac->serdes_link_state = e1000_serdes_link_down;

			e_dbg("ANYSTATE  -> DOWN\n");

		} else {

			/*

			 * Check several times, if SYNCH bit and CONFIG

			/* Check several times, if SYNCH bit and CONFIG

			 * bit both are consistently 1 then simply ignore

			 * the IV bit and restart Autoneg

			 */

	/* If workaround is activated... */

	if (state)

		/*

		 * Hold a copy of the LAA in RAR[14] This is done so that

		/* Hold a copy of the LAA in RAR[14] This is done so that

		 * between the time RAR[0] gets clobbered and the time it

		 * gets fixed, the actual LAA is in one of the RARs and no

		 * incoming packets directed to this port are dropped.

	if (nvm->type != e1000_nvm_flash_hw)

		return 0;

	/*

	 * Check bit 4 of word 10h.  If it is 0, firmware is done updating

	/* Check bit 4 of word 10h.  If it is 0, firmware is done updating

	 * 10h-12h.  Checksum may need to be fixed.

	 */

	ret_val = e1000_read_nvm(hw, 0x10, 1, &data);

		return ret_val;

	if (!(data & 0x10)) {

		/*

		 * Read 0x23 and check bit 15.  This bit is a 1

		/* Read 0x23 and check bit 15.  This bit is a 1

		 * when the checksum has already been fixed.  If

		 * the checksum is still wrong and this bit is a

		 * 1, we need to return bad checksum.  Otherwise,

	if (hw->mac.type == e1000_82571) {

		s32 ret_val = 0;

		/*

		 * If there's an alternate MAC address place it in RAR0

		/* If there's an alternate MAC address place it in RAR0

		 * so that it will override the Si installed default perm

		 * address.

		 */

#define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */

#define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */

/*

 * Use byte values for the following shift parameters

/* Use byte values for the following shift parameters

 * Usage:

 *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &

 *                  E1000_PSRCTL_BSIZE0_MASK) |

#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */

#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */

/*

 * Bit definitions for the Management Data IO (MDIO) and Management Data

/* Bit definitions for the Management Data IO (MDIO) and Management Data

 * Clock (MDC) pins in the Device Control Register.

 */

#define E1000_PBA_ECC_STAT_CLR      0x00000002 /* Clear ECC error counter */

#define E1000_PBA_ECC_INT_EN        0x00000004 /* Enable ICR bit 5 for ECC */

/*

 * This defines the bits that are set in the Interrupt Mask

/* This defines the bits that are set in the Interrupt Mask

 * Set/Read Register.  Each bit is documented below:

 *   o RXT0   = Receiver Timer Interrupt (ring 0)

 *   o TXDW   = Transmit Descriptor Written Back

/* 802.1q VLAN Packet Size */

#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */

/* Receive Address */

/*

/* Receive Address

 * Number of high/low register pairs in the RAR. The RAR (Receive Address

 * Registers) holds the directed and multicast addresses that we monitor.

 * Technically, we have 16 spots.  However, we reserve one of these spots

#define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */

#define MAX_PHY_MULTI_PAGE_REG 0xF

/* Bit definitions for valid PHY IDs. */

/*

/* Bit definitions for valid PHY IDs.

 * I = Integrated

 * E = External

 */

#define M88E1000_PSCR_AUTO_X_1000T     0x0040

/* Auto crossover enabled all speeds */

#define M88E1000_PSCR_AUTO_X_MODE      0x0060

/*

 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold)

/* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold)

 * 0=Normal 10BASE-T Rx Threshold

 */

#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */

#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7

/*

 * Number of times we will attempt to autonegotiate before downshifting if we

/* Number of times we will attempt to autonegotiate before downshifting if we

 * are the master

 */

#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00

#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000

/*

 * Number of times we will attempt to autonegotiate before downshifting if we

/* Number of times we will attempt to autonegotiate before downshifting if we

 * are the slave

 */

#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300

#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \

                           ((reg) & MAX_PHY_REG_ADDRESS))

/*

 * Bits...

/* Bits...

 * 15-5: page

 * 4-0: register offset

 */

/* Time to wait before putting the device into D3 if there's no link (in ms). */

#define LINK_TIMEOUT		100

/*

 * Count for polling __E1000_RESET condition every 10-20msec.

/* Count for polling __E1000_RESET condition every 10-20msec.

 * Experimentation has shown the reset can take approximately 210msec.

 */

#define E1000_CHECK_RESET_COUNT		25

#define BURST_RDTR			0x20

#define BURST_RADV			0x20

/*

 * in the case of WTHRESH, it appears at least the 82571/2 hardware

/* in the case of WTHRESH, it appears at least the 82571/2 hardware

 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when

 * WTHRESH=4, so a setting of 5 gives the most efficient bus

 * utilization but to avoid possible Tx stalls, set it to 1

	u64 dma; /* must be u64 - written to hw */

};

/*

 * wrappers around a pointer to a socket buffer,

/* wrappers around a pointer to a socket buffer,

 * so a DMA handle can be stored along with the buffer

 */

struct e1000_buffer {

	u16 tx_itr;

	u16 rx_itr;

	/*

	 * Tx

	 */

	/* Tx */

	struct e1000_ring *tx_ring /* One per active queue */

						____cacheline_aligned_in_smp;

	u32 tx_fifo_limit;

	u32 tx_fifo_size;

	u32 tx_dma_failed;

	/*

	 * Rx

	 */

	/* Rx */

	bool (*clean_rx) (struct e1000_ring *ring, int *work_done,

			  int work_to_do) ____cacheline_aligned_in_smp;

	void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count,