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Commit a1f1e61b authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Readout and check csc_mode

parent daeaaef5
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+2 −2
Original line number Diff line number Diff line
@@ -788,6 +788,8 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
	if (ret)
		return ret;

	crtc_state->csc_mode = 0;

	/* Always allow legacy gamma LUT with no further checking. */
	if (!crtc_state->gamma_enable ||
	    crtc_state_is_legacy_gamma(crtc_state)) {
@@ -814,8 +816,6 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
	else
		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;

	crtc_state->csc_mode = 0;

	if (INTEL_GEN(dev_priv) >= 11) {
		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
		    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
+5 −0
Original line number Diff line number Diff line
@@ -9288,6 +9288,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
		PIPECONF_GAMMA_MODE_SHIFT;

	pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));

	i9xx_get_pipe_color_config(pipe_config);

	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
@@ -9923,6 +9925,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,

	pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));

	pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));

	if (INTEL_GEN(dev_priv) >= 9) {
		u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));

@@ -12234,6 +12238,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
		PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);

		PIPE_CONF_CHECK_X(gamma_mode);
		PIPE_CONF_CHECK_X(csc_mode);
		PIPE_CONF_CHECK_BOOL(gamma_enable);
		PIPE_CONF_CHECK_BOOL(csc_enable);
	}