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Commit a1b161fc authored by Yuanfang Zhang's avatar Yuanfang Zhang Committed by Gerrit - the friendly Code Review server
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byte-cntr: Compatible with ETR sg buff mode 



In ETR sg buff mode, at most 4K data can be obtained
at a time. This change to support this mode.

Change-Id: I26da71e7210f0a85dbd969c6ff047598a1cbddcd
Signed-off-by: default avatarYuanfang Zhang <quic_yuanfang@quicinc.com>
parent 5e3cf80f

drivers/hwtracing/coresight/coresight-byte-cntr.c

+2 −2
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 
#define USB_SG_NUM (USB_BLK_SIZE / PAGE_SIZE)

#define USB_BUF_NUM 255

#define USB_TIME_OUT (5 * HZ)

#define PCIE_BLK_SIZE 32768

#define PCIE_BLK_SIZE 4096



static struct tmc_drvdata *tmcdrvdata;
@@ -766,7 +766,7 @@ static void etr_pcie_write_work_fn(struct work_struct *work) 
		if (!req)

			break;



		tmc_etr_read_bytes(byte_cntr_data, (loff_t *)&byte_cntr_data->offset,

		tmc_etr_read_bytes(byte_cntr_data, &byte_cntr_data->offset,

					PCIE_BLK_SIZE, &actual, &buf);



		if (actual <= 0) {

drivers/hwtracing/coresight/coresight-byte-cntr.h

+1 −1
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ struct byte_cntr { 
	struct mutex		usb_bypass_lock;

	struct mutex		byte_cntr_lock;

	struct coresight_csr		*csr;

	unsigned long		offset;

	loff_t		offset;

	u32			pcie_out_chan;

	struct mhi_dev_client	*out_handle;

	struct work_struct	pcie_open_work;

drivers/hwtracing/coresight/coresight-tmc.c

+1 −1
Original line number Diff line number Diff line
@@ -628,7 +628,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) 


	if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {

		drvdata->out_mode = TMC_ETR_OUT_MODE_MEM;

		 drvdata->pcie_path = TMC_ETR_PCIE_HW_PATH;

		 drvdata->pcie_path = TMC_ETR_PCIE_SW_PATH;

		drvdata->size = tmc_etr_get_default_buffer_size(dev);

	} else {

		drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;