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Commit a190d1c7 authored by Xiaojie Yuan's avatar Xiaojie Yuan Committed by Alex Deucher
Browse files

drm/amdgpu/discovery: add module param for ip discovery enablement 



to control enablement.

Signed-off-by: default avatarXiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 966f1d8f

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -161,6 +161,7 @@ extern int amdgpu_ras_enable; 
extern uint amdgpu_ras_mask;

extern uint amdgpu_ras_mask;

extern int amdgpu_async_gfx_ring;

extern int amdgpu_async_gfx_ring;

extern int amdgpu_mcbp;

extern int amdgpu_mcbp;

extern int amdgpu_discovery;





#ifdef CONFIG_DRM_AMDGPU_SI

#ifdef CONFIG_DRM_AMDGPU_SI

extern int amdgpu_si_support;

extern int amdgpu_si_support;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+10 −0
Original line number Original line Diff line number Diff line
@@ -2578,6 +2578,14 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
	if (amdgpu_mcbp)

	if (amdgpu_mcbp)

		DRM_INFO("MCBP is enabled\n");

		DRM_INFO("MCBP is enabled\n");





	if (amdgpu_discovery) {

		r = amdgpu_discovery_init(adev);

		if (r) {

			dev_err(adev->dev, "amdgpu_discovery_init failed\n");

			return r;

		}

	}



	/* early init functions */

	/* early init functions */

	r = amdgpu_device_ip_early_init(adev);

	r = amdgpu_device_ip_early_init(adev);

	if (r)

	if (r)
@@ -2838,6 +2846,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev) 
	amdgpu_ucode_sysfs_fini(adev);

	amdgpu_ucode_sysfs_fini(adev);

	amdgpu_pmu_fini(adev);

	amdgpu_pmu_fini(adev);

	amdgpu_debugfs_preempt_cleanup(adev);

	amdgpu_debugfs_preempt_cleanup(adev);

	if (amdgpu_discovery)

		amdgpu_discovery_fini(adev);

}

}

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -138,6 +138,7 @@ uint amdgpu_smu_memory_pool_size = 0; 
uint amdgpu_dc_feature_mask = 0;

uint amdgpu_dc_feature_mask = 0;

int amdgpu_async_gfx_ring = 1;

int amdgpu_async_gfx_ring = 1;

int amdgpu_mcbp = 0;

int amdgpu_mcbp = 0;

int amdgpu_discovery = 0;





struct amdgpu_mgpu_info mgpu_info = {

struct amdgpu_mgpu_info mgpu_info = {

	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),

	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
@@ -579,6 +580,10 @@ MODULE_PARM_DESC(mcbp, 
	"Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");

	"Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");

module_param_named(mcbp, amdgpu_mcbp, int, 0444);

module_param_named(mcbp, amdgpu_mcbp, int, 0444);





MODULE_PARM_DESC(discovery,

	"Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");

module_param_named(discovery, amdgpu_discovery, int, 0444);



#ifdef CONFIG_HSA_AMD

#ifdef CONFIG_HSA_AMD

/**

/**

 * DOC: sched_policy (int)

 * DOC: sched_policy (int)