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Commit a18bf0ca authored by hersen wu's avatar hersen wu Committed by Alex Deucher
Browse files

drm/amd/powrplay: add interface for dc to get max clock values 



dc (display component) needs maximum clock values of uclock,
socclk, dcefclk, to calculate display bandwidth.

Signed-off-by: default avatarhersen wu <hersenxs.wu@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6fbefb84

drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

+4 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include "amdgpu.h"

#include "kgd_pp_interface.h"

#include "dm_pp_interface.h"

#include "dm_pp_smu.h"



#define SMU_THERMAL_MINIMUM_ALERT_TEMP		0

#define SMU_THERMAL_MAXIMUM_ALERT_TEMP		255
@@ -678,6 +679,7 @@ struct smu_funcs 
	int (*gfx_off_control)(struct smu_context *smu, bool enable);

	int (*register_irq_handler)(struct smu_context *smu);

	int (*set_azalia_d3_pme)(struct smu_context *smu);

	int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);

};



#define smu_init_microcode(smu) \
@@ -884,6 +886,8 @@ struct smu_funcs 
	((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0)

#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \

	((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)

#define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \

	((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)



extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,

				   uint16_t *size, uint8_t *frev, uint8_t *crev,

drivers/gpu/drm/amd/powerplay/smu_v11_0.c

+31 −0
Original line number Diff line number Diff line
@@ -1598,6 +1598,36 @@ static int smu_v11_0_register_irq_handler(struct smu_context *smu) 
	return ret;

}



static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,

		struct pp_smu_nv_clock_table *max_clocks)

{

	struct smu_table_context *table_context = &smu->smu_table;

	struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;



	if (!max_clocks || !table_context->max_sustainable_clocks)

		return -EINVAL;



	sustainable_clocks = table_context->max_sustainable_clocks;



	max_clocks->dcfClockInKhz =

			(unsigned int) sustainable_clocks->dcef_clock * 1000;

	max_clocks->displayClockInKhz =

			(unsigned int) sustainable_clocks->display_clock * 1000;

	max_clocks->phyClockInKhz =

			(unsigned int) sustainable_clocks->phy_clock * 1000;

	max_clocks->pixelClockInKhz =

			(unsigned int) sustainable_clocks->pixel_clock * 1000;

	max_clocks->uClockInKhz =

			(unsigned int) sustainable_clocks->uclock * 1000;

	max_clocks->socClockInKhz =

			(unsigned int) sustainable_clocks->soc_clock * 1000;

	max_clocks->dscClockInKhz = 0;

	max_clocks->dppClockInKhz = 0;

	max_clocks->fabricClockInKhz = 0;



	return 0;

}



static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)

{

	int ret = 0;
@@ -1656,6 +1686,7 @@ static const struct smu_funcs smu_v11_0_funcs = { 
	.gfx_off_control = smu_v11_0_gfx_off_control,

	.register_irq_handler = smu_v11_0_register_irq_handler,

	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,

	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,

};



void smu_v11_0_set_smu_funcs(struct smu_context *smu)