Loading qcom/lahaina.dtsi +68 −0 Original line number Diff line number Diff line Loading @@ -2861,6 +2861,74 @@ clock-names = "km_clk_src"; clocks = <&clock_rpmh RPMH_HWKM_CLK>; }; qcom_cedev: qcedev@1de0000 { compatible = "qcom,qcedev"; reg = <0x1de0000 0x20000>, <0x1dc4000 0x24000>; reg-names = "crypto-base","crypto-bam-base"; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; qcom,bam-pipe-pair = <3>; qcom,ce-hw-instance = <0>; qcom,ce-device = <0>; qcom,ce-hw-shared; qcom,bam-ee = <0>; qcom,smmu-s1-enable; qcom,no-clock-support; interconnect-names = "data_path"; interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; iommus = <&apps_smmu 0x0586 0x0011>, <&apps_smmu 0x0596 0x0011>; qcom,iommu-dma = "atomic"; qcom_cedev_ns_cb { compatible = "qcom,qcedev,context-bank"; label = "ns_context"; iommus = <&apps_smmu 0x592 0>, <&apps_smmu 0x598 0>, <&apps_smmu 0x599 0>, <&apps_smmu 0x59F 0>; }; qcom_cedev_s_cb { compatible = "qcom,qcedev,context-bank"; label = "secure_context"; iommus = <&apps_smmu 0x593 0>, <&apps_smmu 0x59C 0>, <&apps_smmu 0x59D 0>, <&apps_smmu 0x59E 0>; qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ qcom,secure-context-bank; }; }; qcom_crypto: qcrypto@1de0000 { compatible = "qcom,qcrypto"; reg = <0x1de0000 0x20000>, <0x1dc4000 0x24000>; reg-names = "crypto-base","crypto-bam-base"; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; qcom,bam-pipe-pair = <2>; qcom,ce-hw-instance = <0>; qcom,ce-device = <0>; qcom,bam-ee = <0>; qcom,ce-hw-shared; qcom,clk-mgmt-sus-res; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; qcom,use-sw-ahash-algo; qcom,use-sw-aead-algo; qcom,use-sw-hmac-algo; qcom,smmu-s1-enable; qcom,no-clock-support; interconnect-names = "data_path"; interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; iommus = <&apps_smmu 0x0584 0x0011>, <&apps_smmu 0x0594 0x0011>; qcom,iommu-dma = "atomic"; }; }; #include "lahaina-regulators.dtsi" Loading Loading
qcom/lahaina.dtsi +68 −0 Original line number Diff line number Diff line Loading @@ -2861,6 +2861,74 @@ clock-names = "km_clk_src"; clocks = <&clock_rpmh RPMH_HWKM_CLK>; }; qcom_cedev: qcedev@1de0000 { compatible = "qcom,qcedev"; reg = <0x1de0000 0x20000>, <0x1dc4000 0x24000>; reg-names = "crypto-base","crypto-bam-base"; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; qcom,bam-pipe-pair = <3>; qcom,ce-hw-instance = <0>; qcom,ce-device = <0>; qcom,ce-hw-shared; qcom,bam-ee = <0>; qcom,smmu-s1-enable; qcom,no-clock-support; interconnect-names = "data_path"; interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; iommus = <&apps_smmu 0x0586 0x0011>, <&apps_smmu 0x0596 0x0011>; qcom,iommu-dma = "atomic"; qcom_cedev_ns_cb { compatible = "qcom,qcedev,context-bank"; label = "ns_context"; iommus = <&apps_smmu 0x592 0>, <&apps_smmu 0x598 0>, <&apps_smmu 0x599 0>, <&apps_smmu 0x59F 0>; }; qcom_cedev_s_cb { compatible = "qcom,qcedev,context-bank"; label = "secure_context"; iommus = <&apps_smmu 0x593 0>, <&apps_smmu 0x59C 0>, <&apps_smmu 0x59D 0>, <&apps_smmu 0x59E 0>; qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ qcom,secure-context-bank; }; }; qcom_crypto: qcrypto@1de0000 { compatible = "qcom,qcrypto"; reg = <0x1de0000 0x20000>, <0x1dc4000 0x24000>; reg-names = "crypto-base","crypto-bam-base"; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; qcom,bam-pipe-pair = <2>; qcom,ce-hw-instance = <0>; qcom,ce-device = <0>; qcom,bam-ee = <0>; qcom,ce-hw-shared; qcom,clk-mgmt-sus-res; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; qcom,use-sw-ahash-algo; qcom,use-sw-aead-algo; qcom,use-sw-hmac-algo; qcom,smmu-s1-enable; qcom,no-clock-support; interconnect-names = "data_path"; interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; iommus = <&apps_smmu 0x0584 0x0011>, <&apps_smmu 0x0594 0x0011>; qcom,iommu-dma = "atomic"; }; }; #include "lahaina-regulators.dtsi" Loading