Merge "dt-bindings: clock: Add support for clock ids for SDXNIGHTJAR" (a15fa3b0) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/clk/qcom/clk-smd-rpm.c

+84 −2

Original line number	Diff line number	Diff line
		@@ -878,6 +878,69 @@ static const struct rpm_smd_clk_desc rpm_clk_holi = {
		.num_clks = ARRAY_SIZE(holi_clks),
		};

		DEFINE_CLK_SMD_RPM(sdxnightjar, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
		DEFINE_CLK_SMD_RPM(sdxnightjar, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);

		/* SMD_XO_BUFFER */
		DEFINE_CLK_SMD_RPM_XO_BUFFER(sdxnightjar, ln_bb_clk, ln_bb_clk_a,
		QCOM_SMD_RPM_CLK_BUF_A, 8);
		DEFINE_CLK_SMD_RPM_XO_BUFFER(sdxnightjar, div_clk1, div_clk1_a,
		QCOM_SMD_RPM_CLK_BUF_A, 0xb);
		DEFINE_CLK_SMD_RPM_XO_BUFFER(sdxnightjar, rf_clk1, rf_clk1_a,
		QCOM_SMD_RPM_CLK_BUF_A, 4);
		DEFINE_CLK_SMD_RPM_XO_BUFFER(sdxnightjar, rf_clk2, rf_clk2_a,
		QCOM_SMD_RPM_CLK_BUF_A, 5);
		DEFINE_CLK_SMD_RPM_XO_BUFFER(sdxnightjar, rf_clk3, rf_clk3_a,
		QCOM_SMD_RPM_CLK_BUF_A, 6);

		DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdxnightjar, rf_clk1_pin, rf_clk1_a_pin,
		QCOM_SMD_RPM_CLK_BUF_A, 4);
		DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdxnightjar, rf_clk2_pin, rf_clk2_a_pin,
		QCOM_SMD_RPM_CLK_BUF_A, 5);
		DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdxnightjar, rf_clk3_pin, rf_clk3_a_pin,
		QCOM_SMD_RPM_CLK_BUF_A, 6);

		/* SDXNIGHTJAR */
		static struct clk_hw *sdxnightjar_clks[] = {
		[RPM_SMD_XO_CLK_SRC] = &holi_bi_tcxo.hw,
		[RPM_SMD_XO_A_CLK_SRC] = &holi_bi_tcxo_ao.hw,
		[RPM_SMD_SNOC_CLK] = &sdxnightjar_snoc_clk.hw,
		[RPM_SMD_SNOC_A_CLK] = &sdxnightjar_snoc_a_clk.hw,
		[RPM_SMD_BIMC_CLK] = &holi_bimc_clk.hw,
		[RPM_SMD_BIMC_A_CLK] = &holi_bimc_a_clk.hw,
		[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk.hw,
		[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk.hw,
		[RPM_SMD_IPA_CLK] = &holi_ipa_clk.hw,
		[RPM_SMD_IPA_A_CLK] = &holi_ipa_a_clk.hw,
		[RPM_SMD_CE1_CLK] = &holi_ce1_clk.hw,
		[RPM_SMD_CE1_A_CLK] = &holi_ce1_a_clk.hw,
		[RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk.hw,
		[RPM_SMD_QPIC_A_CLK] = &qcs404_qpic_a_clk.hw,
		[RPM_SMD_PCNOC_CLK] = &sdxnightjar_pcnoc_clk.hw,
		[RPM_SMD_PCNOC_A_CLK] = &sdxnightjar_pcnoc_a_clk.hw,
		[RPM_SMD_LN_BB_CLK] = &sdxnightjar_ln_bb_clk.hw,
		[RPM_SMD_LN_BB_CLK_A] = &sdxnightjar_ln_bb_clk_a.hw,
		[RPM_SMD_DIV_CLK1] = &sdxnightjar_div_clk1.hw,
		[RPM_SMD_DIV_A_CLK1] = &sdxnightjar_div_clk1_a.hw,
		[RPM_SMD_RF_CLK1] = &sdxnightjar_rf_clk1.hw,
		[RPM_SMD_RF_CLK1_A] = &sdxnightjar_rf_clk1_a.hw,
		[RPM_SMD_RF_CLK2] = &sdxnightjar_rf_clk2.hw,
		[RPM_SMD_RF_CLK2_A] = &sdxnightjar_rf_clk2_a.hw,
		[RPM_SMD_RF_CLK3] = &sdxnightjar_rf_clk3.hw,
		[RPM_SMD_RF_CLK3_A] = &sdxnightjar_rf_clk3_a.hw,
		[RPM_SMD_RF_CLK1_PIN] = &sdxnightjar_rf_clk1_pin.hw,
		[RPM_SMD_RF_CLK1_A_PIN] = &sdxnightjar_rf_clk1_a_pin.hw,
		[RPM_SMD_RF_CLK2_PIN] = &sdxnightjar_rf_clk2_pin.hw,
		[RPM_SMD_RF_CLK2_A_PIN] = &sdxnightjar_rf_clk2_a_pin.hw,
		[RPM_SMD_RF_CLK3_PIN] = &sdxnightjar_rf_clk3_pin.hw,
		[RPM_SMD_RF_CLK3_A_PIN] = &sdxnightjar_rf_clk3_a_pin.hw,
		};

		static const struct rpm_smd_clk_desc rpm_clk_sdxnightjar = {
		.clks = sdxnightjar_clks,
		.num_clks = ARRAY_SIZE(sdxnightjar_clks),
		};

		static const struct of_device_id rpm_smd_clk_match_table[] = {
		{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
		{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
		@@ -885,6 +948,7 @@ static const struct of_device_id rpm_smd_clk_match_table[] = {
		{ .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
		{ .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 },
		{ .compatible = "qcom,rpmcc-holi", .data = &rpm_clk_holi},
		{ .compatible = "qcom,rpmcc-sdxnightjar", .data = &rpm_clk_sdxnightjar},
		{ }
		};
		MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
		@@ -943,7 +1007,7 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
		{
		struct clk_hw **hw_clks;
		const struct rpm_smd_clk_desc *desc;
		int ret, i, is_holi, hw_clk_handoff = false;
		int ret, i, is_holi, hw_clk_handoff = false, is_sdxnightjar;

		desc = of_device_get_match_data(&pdev->dev);
		if (!desc)
		@@ -951,7 +1015,9 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)

		is_holi = of_device_is_compatible(pdev->dev.of_node,
		"qcom,rpmcc-holi");
		if (is_holi) {
		is_sdxnightjar = of_device_is_compatible(pdev->dev.of_node,
		"qcom,rpmcc-sdxnightjar");
		if (is_holi \|\| is_sdxnightjar) {
		ret = clk_vote_bimc(&holi_bimc_clk.hw, INT_MAX);
		if (ret < 0)
		return ret;
		@@ -1011,6 +1077,22 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
		clk_set_rate(holi_snoc_a_clk.hw.clk, 19200000);
		}

		if (is_sdxnightjar) {
		/*
		* Keep an active vote on CXO in case no other driver
		* votes for it.
		*/
		clk_prepare_enable(holi_bi_tcxo_ao.hw.clk);

		/* Hold an active set vote for the pcnoc_keepalive_a_clk */
		clk_prepare_enable(sdxnightjar_pcnoc_a_clk.hw.clk);
		clk_set_rate(sdxnightjar_pcnoc_a_clk.hw.clk, 19200000);

		/* Hold an active set vote for the snoc_keepalive_a_clk */
		clk_prepare_enable(sdxnightjar_snoc_a_clk.hw.clk);
		clk_set_rate(sdxnightjar_snoc_a_clk.hw.clk, 19200000);
		}

		if (of_property_read_bool(pdev->dev.of_node, "qcom,bimc-log-stop"))
		atomic_notifier_chain_register(&panic_notifier_list,
		&smd_rpm_clk_panic_notifier);

include/dt-bindings/clock/qcom,gcc-sdxnightjar.h

0 → 100644

+90 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0-only */
		/*
		* Copyright (c) 2020, The Linux Foundation. All rights reserved.
		*/

		#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDXNIGHTJAR_H
		#define _DT_BINDINGS_CLK_QCOM_GCC_SDXNIGHTJAR_H

		/* GCC clocks */
		#define GPLL0 0
		#define GPLL0_AO 1
		#define GPLL0_OUT_MAIN_DIV2 2
		#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3
		#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4
		#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5
		#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6
		#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7
		#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8
		#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9
		#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10
		#define BLSP1_UART1_APPS_CLK_SRC 11
		#define BLSP1_UART2_APPS_CLK_SRC 12
		#define BLSP1_UART3_APPS_CLK_SRC 13
		#define BLSP1_UART4_APPS_CLK_SRC 14
		#define GCC_APSS_TCU_CLK 15
		#define GCC_BLSP1_AHB_CLK 16
		#define GCC_BLSP1_QUP1_I2C_APPS_CLK 17
		#define GCC_BLSP1_QUP1_SPI_APPS_CLK 18
		#define GCC_BLSP1_QUP2_I2C_APPS_CLK 19
		#define GCC_BLSP1_QUP2_SPI_APPS_CLK 20
		#define GCC_BLSP1_QUP3_I2C_APPS_CLK 21
		#define GCC_BLSP1_QUP3_SPI_APPS_CLK 22
		#define GCC_BLSP1_QUP4_I2C_APPS_CLK 23
		#define GCC_BLSP1_QUP4_SPI_APPS_CLK 24
		#define GCC_BLSP1_SLEEP_CLK 25
		#define GCC_BLSP1_UART1_APPS_CLK 26
		#define GCC_BLSP1_UART2_APPS_CLK 27
		#define GCC_BLSP1_UART3_APPS_CLK 28
		#define GCC_BLSP1_UART4_APPS_CLK 29
		#define GCC_BOOT_ROM_AHB_CLK 30
		#define GCC_DCC_CLK 31
		#define GCC_GP1_CLK 32
		#define GCC_GP2_CLK 33
		#define GCC_GP3_CLK 34
		#define GCC_MSS_GPLL0_CLK_SRC 35
		#define GCC_PCIE_AXI_CLK 36
		#define GCC_PCIE_AXI_MSTR_CLK 37
		#define GCC_PCIE_AXI_TBU_CLK 38
		#define GCC_PCIE_CFG_AHB_CLK 39
		#define GCC_PCIE_REF_CLK 40
		#define GCC_PCIE_PIPE_CLK 41
		#define GCC_PCIE_SLEEP_CLK 42
		#define GCC_PDM2_CLK 43
		#define GCC_PDM_AHB_CLK 44
		#define GCC_PDM_XO4_CLK 45
		#define GCC_PRNG_AHB_CLK 46
		#define GCC_QUSB_REF_CLK 47
		#define GCC_SDCC1_AHB_CLK 48
		#define GCC_SDCC1_APPS_CLK 49
		#define GCC_SMMU_CFG_CLK 50
		#define GCC_SYS_NOC_USB3_AXI_CLK 51
		#define GCC_USB30_MASTER_CLK 52
		#define GCC_USB30_MOCK_UTMI_CLK 53
		#define GCC_USB30_SLEEP_CLK 54
		#define GCC_USB3_AUX_CLK 55
		#define GCC_USB3_AXI_TBU_CLK 56
		#define GCC_USB3_PIPE_CLK 57
		#define GCC_USB_PHY_CFG_AHB_CLK 58
		#define GCC_USB_SS_REF_CLK 59
		#define GCC_XO_DIV4_CLK 60
		#define GP1_CLK_SRC 61
		#define GP2_CLK_SRC 62
		#define GP3_CLK_SRC 63
		#define PCIE_AUX_CLK_SRC 64
		#define PDM2_CLK_SRC 65
		#define SDCC1_APPS_CLK_SRC 66
		#define USB30_MASTER_CLK_SRC 67
		#define USB30_MOCK_UTMI_CLK_SRC 68
		#define USB3_AUX_CLK_SRC 69
		#define APSS_AHB_CLK_SRC 70

		/* GCC resets */
		#define GCC_PCIEPHY_PHY_BCR 0
		#define GCC_PCIE_PHY_BCR 1
		#define GCC_USB_30_BCR 2
		#define GCC_USB3_PHY_BCR 3
		#define GCC_USB3PHY_PHY_BCR 4
		#define GCC_QUSB2A_PHY_BCR 5

		#endif