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Commit a14b1652 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add flag to support cfgready signal bypass sw workaround"

parents 9ff64161 8ff06cbe

qcom/shima.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -1216,6 +1216,9 @@ 
		phy-names = "ufsphy";

		#reset-cells = <1>;



		/* UFS gear4 cfgReady bypass WA */

		bypass-g4-cfgready;



		lanes-per-direction = <2>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */

		clock-names =