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Commit a1406b72 authored by Anson Huang's avatar Anson Huang Committed by Shawn Guo
Browse files

arm64: dts: imx8mm: Enable cpu-idle driver 



Enable i.MX8MM cpu-idle using generic ARM cpu-idle driver, 2 states
are supported, details as below:

root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/name
WFI
root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/usage
3973
root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/name
cpu-pd-wait
root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
6647

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Acked-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 491d3a3f

arch/arm64/boot/dts/freescale/imx8mm.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -44,6 +44,19 @@ 
		#address-cells = <1>;

		#size-cells = <0>;



		idle-states {

			entry-method = "psci";



			cpu_pd_wait: cpu-pd-wait {

				compatible = "arm,idle-state";

				arm,psci-suspend-param = <0x0010033>;

				local-timer-stop;

				entry-latency-us = <1000>;

				exit-latency-us = <700>;

				min-residency-us = <2700>;

			};

		};



		A53_0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";
@@ -55,6 +68,7 @@ 
			operating-points-v2 = <&a53_opp_table>;

			nvmem-cells = <&cpu_speed_grade>;

			nvmem-cell-names = "speed_grade";

			cpu-idle-states = <&cpu_pd_wait>;

		};



		A53_1: cpu@1 {
@@ -66,6 +80,7 @@ 
			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			operating-points-v2 = <&a53_opp_table>;

			cpu-idle-states = <&cpu_pd_wait>;

		};



		A53_2: cpu@2 {
@@ -77,6 +92,7 @@ 
			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			operating-points-v2 = <&a53_opp_table>;

			cpu-idle-states = <&cpu_pd_wait>;

		};



		A53_3: cpu@3 {
@@ -88,6 +104,7 @@ 
			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			operating-points-v2 = <&a53_opp_table>;

			cpu-idle-states = <&cpu_pd_wait>;

		};



		A53_L2: l2-cache0 {