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Commit a1304d35 authored by Joseph Lo's avatar Joseph Lo Committed by Thierry Reding
Browse files

arm64: tegra: Enable DFLL clock on Jetson TX1 



Enable DFLL clock for Jetson TX1 platform.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Acked-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent a5e98b0b

arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts

+21 −0
Original line number Diff line number Diff line
@@ -78,4 +78,25 @@ 
			};

		};

	};



	clock@70110000 {

		status = "okay";



		nvidia,cf = <6>;

		nvidia,ci = <0>;

		nvidia,cg = <2>;

		nvidia,droop-ctrl = <0x00000f00>;

		nvidia,force-mode = <1>;

		nvidia,sample-rate = <25000>;



		nvidia,pwm-min-microvolts = <708000>;

		nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */

		nvidia,pwm-to-pmic;

		nvidia,pwm-tristate-microvolts = <1000000>;

		nvidia,pwm-voltage-step-microvolts = <19200>;



		pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";

		pinctrl-0 = <&dvfs_pwm_active_state>;

		pinctrl-1 = <&dvfs_pwm_inactive_state>;

	};

};