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Commit a129d92f authored by Jayamohan Kallickal's avatar Jayamohan Kallickal Committed by James Bottomley
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[SCSI] be2iscsi: Fix Template HDR support for Dual Chute mode



Template HDR is created for each chute which has iSCSI Protocol loaded.
For BE-X family iSCSI protocol is loaded only on single chute.

Signed-off-by: default avatarJohn Soni Jose <sony.john-n@emulex.com>
Signed-off-by: default avatarJayamohan Kallickal <jayamohan.kallickal@emulex.com>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent 8a86e833
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+26 −17
Original line number Diff line number Diff line
@@ -2539,8 +2539,6 @@ static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
		phba->params.icds_per_ctrl;
	phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
		phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
	phba->mem_req[HWI_MEM_TEMPLATE_HDR] = phba->params.cxns_per_ctrl *
					      BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE;
	for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
		if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {

@@ -2564,6 +2562,12 @@ static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
					       phba, ulp_num) *
					       sizeof(struct phys_addr));

			mem_descr_index = (HWI_MEM_TEMPLATE_HDR_ULP0 +
					  (ulp_num * MEM_DESCR_OFFSET));
			phba->mem_req[mem_descr_index] =
					BEISCSI_GET_CID_COUNT(phba, ulp_num) *
					BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE;

			mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
					  (ulp_num * MEM_DESCR_OFFSET));
			phba->mem_req[mem_descr_index] =
@@ -3405,26 +3409,31 @@ beiscsi_post_template_hdr(struct beiscsi_hba *phba)
	struct be_mem_descriptor *mem_descr;
	struct mem_array *pm_arr;
	struct be_dma_mem sgl;
	int status, i;
	int status, ulp_num;

	mem_descr = phba->init_mem;
	mem_descr += HWI_MEM_TEMPLATE_HDR;
	for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
		if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
			mem_descr = (struct be_mem_descriptor *)phba->init_mem;
			mem_descr += HWI_MEM_TEMPLATE_HDR_ULP0 +
				    (ulp_num * MEM_DESCR_OFFSET);
			pm_arr = mem_descr->mem_array;

	for (i = 0; i < mem_descr->num_elements; i++) {
			hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
		status = be_cmd_iscsi_post_template_hdr(&phba->ctrl, &sgl);
			status = be_cmd_iscsi_post_template_hdr(
				 &phba->ctrl, &sgl);

			if (status != 0) {
				beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
				    "BM_%d : Post Template HDR Failed\n");
					    "BM_%d : Post Template HDR Failed for"
					    "ULP_%d\n", ulp_num);
				return status;
			}
	}

			beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
		    "BM_%d : Template HDR Pages Posted\n");

				    "BM_%d : Template HDR Pages Posted for"
				    "ULP_%d\n", ulp_num);
		}
	}
	return 0;
}

+7 −6
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@

#define BEISCSI_MSI_NAME 20 /* size of msi_name string */

#define MEM_DESCR_OFFSET 7
#define MEM_DESCR_OFFSET 8
#define BEISCSI_DEFQ_HDR 1
#define BEISCSI_DEFQ_DATA 0
enum be_mem_enum {
@@ -170,20 +170,21 @@ enum be_mem_enum {
	HWI_MEM_WRBH,
	HWI_MEM_SGLH,
	HWI_MEM_SGE,
	HWI_MEM_TEMPLATE_HDR,
	HWI_MEM_ASYNC_HEADER_BUF_ULP0,
	HWI_MEM_TEMPLATE_HDR_ULP0,
	HWI_MEM_ASYNC_HEADER_BUF_ULP0,	/* 6 */
	HWI_MEM_ASYNC_DATA_BUF_ULP0,
	HWI_MEM_ASYNC_HEADER_RING_ULP0,
	HWI_MEM_ASYNC_DATA_RING_ULP0,
	HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
	HWI_MEM_ASYNC_DATA_HANDLE_ULP0,
	HWI_MEM_ASYNC_DATA_HANDLE_ULP0,	/* 11 */
	HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
	HWI_MEM_ASYNC_HEADER_BUF_ULP1,
	HWI_MEM_TEMPLATE_HDR_ULP1,
	HWI_MEM_ASYNC_HEADER_BUF_ULP1,	/* 14 */
	HWI_MEM_ASYNC_DATA_BUF_ULP1,
	HWI_MEM_ASYNC_HEADER_RING_ULP1,
	HWI_MEM_ASYNC_DATA_RING_ULP1,
	HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
	HWI_MEM_ASYNC_DATA_HANDLE_ULP1,
	HWI_MEM_ASYNC_DATA_HANDLE_ULP1,	/* 19 */
	HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
	ISCSI_MEM_GLOBAL_HEADER,
	SE_MEM_MAX