Loading drivers/gpu/msm/adreno-gpulist.h +9 −7 Original line number Diff line number Diff line Loading @@ -1078,9 +1078,10 @@ static const struct a6xx_protected_regs a620_protected_regs[] = { { A6XX_CP_PROTECT_REG + 32, 0x0fc00, 0x11bff, 0 }, { A6XX_CP_PROTECT_REG + 33, 0x18400, 0x1a3ff, 1 }, { A6XX_CP_PROTECT_REG + 34, 0x1a800, 0x1c7ff, 1 }, { A6XX_CP_PROTECT_REG + 35, 0x1f400, 0x1f843, 1 }, { A6XX_CP_PROTECT_REG + 36, 0x1f844, 0x1f8bf, 0 }, { A6XX_CP_PROTECT_REG + 37, 0x1f887, 0x1f8a2, 1 }, { A6XX_CP_PROTECT_REG + 35, 0x1c800, 0x1e7ff, 1 }, { A6XX_CP_PROTECT_REG + 36, 0x1f400, 0x1f843, 1 }, { A6XX_CP_PROTECT_REG + 37, 0x1f844, 0x1f8bf, 0 }, { A6XX_CP_PROTECT_REG + 38, 0x1f887, 0x1f8a2, 1 }, { A6XX_CP_PROTECT_REG + 47, 0x1f8c0, 0x1f8c0, 1 }, { 0 }, }; Loading Loading @@ -1609,10 +1610,11 @@ static const struct a6xx_protected_regs a660_protected_regs[] = { { A6XX_CP_PROTECT_REG + 33, 0x0fc00, 0x11bff, 0 }, { A6XX_CP_PROTECT_REG + 34, 0x18400, 0x1a3ff, 1 }, { A6XX_CP_PROTECT_REG + 35, 0x1a400, 0x1c3ff, 1 }, { A6XX_CP_PROTECT_REG + 36, 0x1f400, 0x1f843, 1 }, { A6XX_CP_PROTECT_REG + 37, 0x1f844, 0x1f8bf, 0 }, { A6XX_CP_PROTECT_REG + 38, 0x1f860, 0x1f860, 1 }, { A6XX_CP_PROTECT_REG + 39, 0x1f887, 0x1f8a2, 1 }, { A6XX_CP_PROTECT_REG + 36, 0x1c400, 0x1e3ff, 1 }, { A6XX_CP_PROTECT_REG + 37, 0x1f400, 0x1f843, 1 }, { A6XX_CP_PROTECT_REG + 38, 0x1f844, 0x1f8bf, 0 }, { A6XX_CP_PROTECT_REG + 39, 0x1f860, 0x1f860, 1 }, { A6XX_CP_PROTECT_REG + 40, 0x1f887, 0x1f8a2, 1 }, { A6XX_CP_PROTECT_REG + 47, 0x1f8c0, 0x1f8c0, 1 }, { 0 }, }; Loading Loading
drivers/gpu/msm/adreno-gpulist.h +9 −7 Original line number Diff line number Diff line Loading @@ -1078,9 +1078,10 @@ static const struct a6xx_protected_regs a620_protected_regs[] = { { A6XX_CP_PROTECT_REG + 32, 0x0fc00, 0x11bff, 0 }, { A6XX_CP_PROTECT_REG + 33, 0x18400, 0x1a3ff, 1 }, { A6XX_CP_PROTECT_REG + 34, 0x1a800, 0x1c7ff, 1 }, { A6XX_CP_PROTECT_REG + 35, 0x1f400, 0x1f843, 1 }, { A6XX_CP_PROTECT_REG + 36, 0x1f844, 0x1f8bf, 0 }, { A6XX_CP_PROTECT_REG + 37, 0x1f887, 0x1f8a2, 1 }, { A6XX_CP_PROTECT_REG + 35, 0x1c800, 0x1e7ff, 1 }, { A6XX_CP_PROTECT_REG + 36, 0x1f400, 0x1f843, 1 }, { A6XX_CP_PROTECT_REG + 37, 0x1f844, 0x1f8bf, 0 }, { A6XX_CP_PROTECT_REG + 38, 0x1f887, 0x1f8a2, 1 }, { A6XX_CP_PROTECT_REG + 47, 0x1f8c0, 0x1f8c0, 1 }, { 0 }, }; Loading Loading @@ -1609,10 +1610,11 @@ static const struct a6xx_protected_regs a660_protected_regs[] = { { A6XX_CP_PROTECT_REG + 33, 0x0fc00, 0x11bff, 0 }, { A6XX_CP_PROTECT_REG + 34, 0x18400, 0x1a3ff, 1 }, { A6XX_CP_PROTECT_REG + 35, 0x1a400, 0x1c3ff, 1 }, { A6XX_CP_PROTECT_REG + 36, 0x1f400, 0x1f843, 1 }, { A6XX_CP_PROTECT_REG + 37, 0x1f844, 0x1f8bf, 0 }, { A6XX_CP_PROTECT_REG + 38, 0x1f860, 0x1f860, 1 }, { A6XX_CP_PROTECT_REG + 39, 0x1f887, 0x1f8a2, 1 }, { A6XX_CP_PROTECT_REG + 36, 0x1c400, 0x1e3ff, 1 }, { A6XX_CP_PROTECT_REG + 37, 0x1f400, 0x1f843, 1 }, { A6XX_CP_PROTECT_REG + 38, 0x1f844, 0x1f8bf, 0 }, { A6XX_CP_PROTECT_REG + 39, 0x1f860, 0x1f860, 1 }, { A6XX_CP_PROTECT_REG + 40, 0x1f887, 0x1f8a2, 1 }, { A6XX_CP_PROTECT_REG + 47, 0x1f8c0, 0x1f8c0, 1 }, { 0 }, }; Loading