Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a0a64f50 authored by Xiao Guangrong's avatar Xiao Guangrong Committed by Paolo Bonzini
Browse files

KVM: MMU: introduce rsvd_bits_validate 



These two fields, rsvd_bits_mask and bad_mt_xwr, in "struct kvm_mmu" are
used to check if reserved bits set on guest ptes, move them to a data
struct so that the approach can be applied to check host shadow page
table entries as well

Signed-off-by: default avatarXiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent d2b0f981

arch/x86/include/asm/kvm_host.h

+6 −2
Original line number Diff line number Diff line
@@ -252,6 +252,11 @@ struct kvm_pio_request { 
	int size;

};



struct rsvd_bits_validate {

	u64 rsvd_bits_mask[2][4];

	u64 bad_mt_xwr;

};



/*

 * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level

 * 32-bit).  The kvm_mmu structure abstracts the details of the current mmu
@@ -289,8 +294,7 @@ struct kvm_mmu { 


	u64 *pae_root;

	u64 *lm_root;

	u64 rsvd_bits_mask[2][4];

	u64 bad_mt_xwr;

	struct rsvd_bits_validate guest_rsvd_check;



	/*

	 * Bitmap: bit set = last pte in walk

arch/x86/kvm/mmu.c

+42 −33
Original line number Diff line number Diff line
@@ -3548,10 +3548,11 @@ static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gp 


static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)

{

	struct rsvd_bits_validate *rsvd_check = &mmu->guest_rsvd_check;

	int bit7 = (gpte >> 7) & 1, low6 = gpte & 0x3f;



	return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) |

		((mmu->bad_mt_xwr & (1ull << low6)) != 0);

	return (gpte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |

		((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);

}



#define PTTYPE_EPT 18 /* arbitrary */
@@ -3570,12 +3571,13 @@ static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) 
static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,

				  struct kvm_mmu *context)

{

	struct rsvd_bits_validate *rsvd_check = &context->guest_rsvd_check;

	int maxphyaddr = cpuid_maxphyaddr(vcpu);

	u64 exb_bit_rsvd = 0;

	u64 gbpages_bit_rsvd = 0;

	u64 nonleaf_bit8_rsvd = 0;



	context->bad_mt_xwr = 0;

	rsvd_check->bad_mt_xwr = 0;



	if (!context->nx)

		exb_bit_rsvd = rsvd_bits(63, 63);
@@ -3592,52 +3594,58 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, 
	switch (context->root_level) {

	case PT32_ROOT_LEVEL:

		/* no rsvd bits for 2 level 4K page table entries */

		context->rsvd_bits_mask[0][1] = 0;

		context->rsvd_bits_mask[0][0] = 0;

		context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];

		rsvd_check->rsvd_bits_mask[0][1] = 0;

		rsvd_check->rsvd_bits_mask[0][0] = 0;

		rsvd_check->rsvd_bits_mask[1][0] =

			rsvd_check->rsvd_bits_mask[0][0];



		if (!is_pse(vcpu)) {

			context->rsvd_bits_mask[1][1] = 0;

			rsvd_check->rsvd_bits_mask[1][1] = 0;

			break;

		}



		if (is_cpuid_PSE36())

			/* 36bits PSE 4MB page */

			context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);

			rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);

		else

			/* 32 bits PSE 4MB page */

			context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);

			rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);

		break;

	case PT32E_ROOT_LEVEL:

		context->rsvd_bits_mask[0][2] =

		rsvd_check->rsvd_bits_mask[0][2] =

			rsvd_bits(maxphyaddr, 63) |

			rsvd_bits(5, 8) | rsvd_bits(1, 2);	/* PDPTE */

		context->rsvd_bits_mask[0][1] = exb_bit_rsvd |

		rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |

			rsvd_bits(maxphyaddr, 62);	/* PDE */

		context->rsvd_bits_mask[0][0] = exb_bit_rsvd |

		rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |

			rsvd_bits(maxphyaddr, 62); 	/* PTE */

		context->rsvd_bits_mask[1][1] = exb_bit_rsvd |

		rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |

			rsvd_bits(maxphyaddr, 62) |

			rsvd_bits(13, 20);		/* large page */

		context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];

		rsvd_check->rsvd_bits_mask[1][0] =

			rsvd_check->rsvd_bits_mask[0][0];

		break;

	case PT64_ROOT_LEVEL:

		context->rsvd_bits_mask[0][3] = exb_bit_rsvd |

			nonleaf_bit8_rsvd | rsvd_bits(7, 7) | rsvd_bits(maxphyaddr, 51);

		context->rsvd_bits_mask[0][2] = exb_bit_rsvd |

			nonleaf_bit8_rsvd | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51);

		context->rsvd_bits_mask[0][1] = exb_bit_rsvd |

		rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |

			nonleaf_bit8_rsvd | rsvd_bits(7, 7) |

			rsvd_bits(maxphyaddr, 51);

		context->rsvd_bits_mask[0][0] = exb_bit_rsvd |

		rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |

			nonleaf_bit8_rsvd | gbpages_bit_rsvd |

			rsvd_bits(maxphyaddr, 51);

		context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];

		context->rsvd_bits_mask[1][2] = exb_bit_rsvd |

		rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |

			rsvd_bits(maxphyaddr, 51);

		rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |

			rsvd_bits(maxphyaddr, 51);

		rsvd_check->rsvd_bits_mask[1][3] =

			rsvd_check->rsvd_bits_mask[0][3];

		rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |

			gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |

			rsvd_bits(13, 29);

		context->rsvd_bits_mask[1][1] = exb_bit_rsvd |

		rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |

			rsvd_bits(maxphyaddr, 51) |

			rsvd_bits(13, 20);		/* large page */

		context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];

		rsvd_check->rsvd_bits_mask[1][0] =

			rsvd_check->rsvd_bits_mask[0][0];

		break;

	}

}
@@ -3645,24 +3653,25 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, 
static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,

		struct kvm_mmu *context, bool execonly)

{

	struct rsvd_bits_validate *rsvd_check = &context->guest_rsvd_check;

	int maxphyaddr = cpuid_maxphyaddr(vcpu);

	int pte;



	context->rsvd_bits_mask[0][3] =

	rsvd_check->rsvd_bits_mask[0][3] =

		rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);

	context->rsvd_bits_mask[0][2] =

	rsvd_check->rsvd_bits_mask[0][2] =

		rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);

	context->rsvd_bits_mask[0][1] =

	rsvd_check->rsvd_bits_mask[0][1] =

		rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);

	context->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);

	rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);



	/* large page */

	context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];

	context->rsvd_bits_mask[1][2] =

	rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];

	rsvd_check->rsvd_bits_mask[1][2] =

		rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);

	context->rsvd_bits_mask[1][1] =

	rsvd_check->rsvd_bits_mask[1][1] =

		rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);

	context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];

	rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];



	for (pte = 0; pte < 64; pte++) {

		int rwx_bits = pte & 7;
@@ -3670,7 +3679,7 @@ static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, 
		if (mt == 0x2 || mt == 0x3 || mt == 0x7 ||

				rwx_bits == 0x2 || rwx_bits == 0x6 ||

				(rwx_bits == 0x4 && !execonly))

			context->bad_mt_xwr |= (1ull << pte);

			rsvd_check->bad_mt_xwr |= (1ull << pte);

	}

}

arch/x86/kvm/x86.c

+2 −1
Original line number Diff line number Diff line
@@ -525,7 +525,8 @@ int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 
	}

	for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {

		if (is_present_gpte(pdpte[i]) &&

		    (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {

		    (pdpte[i] &

		     vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {

			ret = 0;

			goto out;

		}