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Commit 9fbd7fd2 authored by Thomas Gleixner's avatar Thomas Gleixner
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Merge tag 'irqchip-4.14' of... 

Merge tag 'irqchip-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates for 4.14 from Marc Zyngier:

- irqchip-specific part of the monster GICv4 series
- new UniPhier AIDET irqchip driver
- new variants of some Freescale MSI widget
- blanket removal of of_node->full_name in printk
- random collection of fixes
parents b33394ba ae3efabf

Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt

+5 −3
Original line number Original line Diff line number Diff line
@@ -4,8 +4,10 @@ Required properties: 




- compatible: should be "fsl,<soc-name>-msi" to identify

- compatible: should be "fsl,<soc-name>-msi" to identify

	      Layerscape PCIe MSI controller block such as:

	      Layerscape PCIe MSI controller block such as:

              "fsl,1s1021a-msi"

              "fsl,ls1021a-msi"

              "fsl,1s1043a-msi"

              "fsl,ls1043a-msi"

              "fsl,ls1046a-msi"

              "fsl,ls1043a-v1.1-msi"

- msi-controller: indicates that this is a PCIe MSI controller node

- msi-controller: indicates that this is a PCIe MSI controller node

- reg: physical base address of the controller and length of memory mapped.

- reg: physical base address of the controller and length of memory mapped.

- interrupts: an interrupt to the parent interrupt controller.

- interrupts: an interrupt to the parent interrupt controller.
@@ -23,7 +25,7 @@ MSI controller node 
Examples:

Examples:





	msi1: msi-controller@1571000 {

	msi1: msi-controller@1571000 {

		compatible = "fsl,1s1043a-msi";

		compatible = "fsl,ls1043a-msi";

		reg = <0x0 0x1571000 0x0 0x8>,

		reg = <0x0 0x1571000 0x0 0x8>,

		msi-controller;

		msi-controller;

		interrupts = <0 116 0x4>;

		interrupts = <0 116 0x4>;

Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt

0 → 100644
+32 −0
Original line number Original line Diff line number Diff line 
UniPhier AIDET



UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC (Generic

Interrupt Controller).  GIC itself can handle only high level and rising edge

interrupts.  The AIDET provides logic inverter to support low level and falling

edge interrupts.



Required properties:

- compatible: Should be one of the following:

    "socionext,uniphier-ld4-aidet"  - for LD4 SoC

    "socionext,uniphier-pro4-aidet" - for Pro4 SoC

    "socionext,uniphier-sld8-aidet" - for sLD8 SoC

    "socionext,uniphier-pro5-aidet" - for Pro5 SoC

    "socionext,uniphier-pxs2-aidet" - for PXs2/LD6b SoC

    "socionext,uniphier-ld11-aidet" - for LD11 SoC

    "socionext,uniphier-ld20-aidet" - for LD20 SoC

    "socionext,uniphier-pxs3-aidet" - for PXs3 SoC

- reg: Specifies offset and length of the register set for the device.

- interrupt-controller: Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an interrupt

  source.  The value should be 2.  The first cell defines the interrupt number

  (corresponds to the SPI interrupt number of GIC).  The second cell specifies

  the trigger type as defined in interrupts.txt in this directory.



Example:



	aidet: aidet@5fc20000 {

		compatible = "socionext,uniphier-pro4-aidet";

		reg = <0x5fc20000 0x200>;

		interrupt-controller;

		#interrupt-cells = <2>;

	};

MAINTAINERS

+1 −0
Original line number Original line Diff line number Diff line
@@ -1993,6 +1993,7 @@ F: arch/arm64/boot/dts/socionext/ 
F:	drivers/bus/uniphier-system-bus.c

F:	drivers/bus/uniphier-system-bus.c

F:	drivers/clk/uniphier/

F:	drivers/clk/uniphier/

F:	drivers/i2c/busses/i2c-uniphier*

F:	drivers/i2c/busses/i2c-uniphier*

F:	drivers/irqchip/irq-uniphier-aidet.c

F:	drivers/pinctrl/uniphier/

F:	drivers/pinctrl/uniphier/

F:	drivers/reset/reset-uniphier.c

F:	drivers/reset/reset-uniphier.c

F:	drivers/tty/serial/8250/8250_uniphier.c

F:	drivers/tty/serial/8250/8250_uniphier.c

arch/arm/boot/dts/ls1021a.dtsi

+4 −4
Original line number Original line Diff line number Diff line
@@ -129,14 +129,14 @@ 
		};

		};





		msi1: msi-controller@1570e00 {

		msi1: msi-controller@1570e00 {

			compatible = "fsl,1s1021a-msi";

			compatible = "fsl,ls1021a-msi";

			reg = <0x0 0x1570e00 0x0 0x8>;

			reg = <0x0 0x1570e00 0x0 0x8>;

			msi-controller;

			msi-controller;

			interrupts =  <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;

			interrupts =  <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;

		};

		};





		msi2: msi-controller@1570e08 {

		msi2: msi-controller@1570e08 {

			compatible = "fsl,1s1021a-msi";

			compatible = "fsl,ls1021a-msi";

			reg = <0x0 0x1570e08 0x0 0x8>;

			reg = <0x0 0x1570e08 0x0 0x8>;

			msi-controller;

			msi-controller;

			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
@@ -699,7 +699,7 @@ 
			bus-range = <0x0 0xff>;

			bus-range = <0x0 0xff>;

			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */

			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */

				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

			msi-parent = <&msi1>;

			msi-parent = <&msi1>, <&msi2>;

			#interrupt-cells = <1>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,

			interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
@@ -722,7 +722,7 @@ 
			bus-range = <0x0 0xff>;

			bus-range = <0x0 0xff>;

			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */

			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */

				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

			msi-parent = <&msi2>;

			msi-parent = <&msi1>, <&msi2>;

			#interrupt-cells = <1>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,

			interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,

arch/arm/include/asm/arch_gicv3.h

+34 −0
Original line number Original line Diff line number Diff line
@@ -275,6 +275,12 @@ static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr) 
#define gicr_read_pendbaser(c)		__gic_readq_nonatomic(c)

#define gicr_read_pendbaser(c)		__gic_readq_nonatomic(c)

#define gicr_write_pendbaser(v, c)	__gic_writeq_nonatomic(v, c)

#define gicr_write_pendbaser(v, c)	__gic_writeq_nonatomic(v, c)





/*

 * GICR_xLPIR - only the lower bits are significant

 */

#define gic_read_lpir(c)		readl_relaxed(c)

#define gic_write_lpir(v, c)		writel_relaxed(lower_32_bits(v), c)



/*

/*

 * GITS_TYPER is an ID register and doesn't need atomicity.

 * GITS_TYPER is an ID register and doesn't need atomicity.

 */

 */
@@ -291,5 +297,33 @@ static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr) 
 */

 */

#define gits_write_cwriter(v, c)	__gic_writeq_nonatomic(v, c)

#define gits_write_cwriter(v, c)	__gic_writeq_nonatomic(v, c)





/*

 * GITS_VPROPBASER - hi and lo bits may be accessed independently.

 */

#define gits_write_vpropbaser(v, c)	__gic_writeq_nonatomic(v, c)



/*

 * GITS_VPENDBASER - the Valid bit must be cleared before changing

 * anything else.

 */

static inline void gits_write_vpendbaser(u64 val, void * __iomem addr)

{

	u32 tmp;



	tmp = readl_relaxed(addr + 4);

	if (tmp & (GICR_VPENDBASER_Valid >> 32)) {

		tmp &= ~(GICR_VPENDBASER_Valid >> 32);

		writel_relaxed(tmp, addr + 4);

	}



	/*

	 * Use the fact that __gic_writeq_nonatomic writes the second

	 * half of the 64bit quantity after the first.

	 */

	__gic_writeq_nonatomic(val, addr);

}



#define gits_read_vpendbaser(c)		__gic_readq_nonatomic(c)



#endif /* !__ASSEMBLY__ */

#endif /* !__ASSEMBLY__ */

#endif /* !__ASM_ARCH_GICV3_H */
 
#endif /* !__ASM_ARCH_GICV3_H */