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Commit 9fb4bfd0 authored by Sharat Masetty's avatar Sharat Masetty Committed by Rob Clark
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drm/msm/a6xx: Send the right perf index value to GMU 



The index of the perf table was being set in the wrong bit position
in the register. With this fix, the GPU clock can be seen running at
desired frequency.

Signed-off-by: default avatarSharat Masetty <smasetty@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent b689a830

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

+1 −1
Original line number Diff line number Diff line
@@ -70,7 +70,7 @@ static int a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) 
	gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);



	gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,

		((index << 24) & 0xff) | (3 & 0xf));

		((3 & 0xf) << 28) | index);



	/*

	 * Send an invalid index as a vote for the bus bandwidth and let the