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Commit 9fb29c73 authored by Sugaya Taichi's avatar Sugaya Taichi Committed by Arnd Bergmann
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ARM: milbeaut: Add basic support for Milbeaut m10v SoC 



This adds the basic M10V SoC support under arch/arm.
Since all cores are activated in the custom bootloader before booting
linux, it is necessary to wait for the secondary-cores using cpu-enable-
method and special sram.

Signed-off-by: default avatarSugaya Taichi <sugaya.taichi@socionext.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent f2a3aa16

arch/arm/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -750,6 +750,8 @@ source "arch/arm/mach-mediatek/Kconfig" 


source "arch/arm/mach-meson/Kconfig"



source "arch/arm/mach-milbeaut/Kconfig"



source "arch/arm/mach-mmp/Kconfig"



source "arch/arm/mach-moxart/Kconfig"

arch/arm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -190,6 +190,7 @@ machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 
machine-$(CONFIG_ARCH_MVEBU)		+= mvebu

machine-$(CONFIG_ARCH_MXC)		+= imx

machine-$(CONFIG_ARCH_MEDIATEK)		+= mediatek

machine-$(CONFIG_ARCH_MILBEAUT)		+= milbeaut

machine-$(CONFIG_ARCH_MXS)		+= mxs

machine-$(CONFIG_ARCH_NETX)		+= netx

machine-$(CONFIG_ARCH_NOMADIK)		+= nomadik

arch/arm/mach-milbeaut/Kconfig

0 → 100644
+20 −0
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# SPDX-License-Identifier: GPL-2.0

menuconfig ARCH_MILBEAUT

	bool "Socionext Milbeaut SoCs"

	depends on ARCH_MULTI_V7

	select ARM_GIC

	help

	  This enables support for Socionext Milbeaut SoCs



if ARCH_MILBEAUT



config ARCH_MILBEAUT_M10V

	bool "Milbeaut SC2000/M10V platform"

	select ARM_ARCH_TIMER

	select MILBEAUT_TIMER

	select PINCTRL

	select PINCTRL_MILBEAUT

	help

	  Support for Socionext's MILBEAUT M10V based systems



endif

arch/arm/mach-milbeaut/Makefile

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+1 −0
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obj-$(CONFIG_SMP) += platsmp.o

arch/arm/mach-milbeaut/platsmp.c

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+143 −0
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// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright:	(C) 2018 Socionext Inc.

 * Copyright:	(C) 2015 Linaro Ltd.

 */



#include <linux/cpu_pm.h>

#include <linux/irqchip/arm-gic.h>

#include <linux/of_address.h>

#include <linux/suspend.h>



#include <asm/cacheflush.h>

#include <asm/cp15.h>

#include <asm/idmap.h>

#include <asm/smp_plat.h>

#include <asm/suspend.h>



#define M10V_MAX_CPU	4

#define KERNEL_UNBOOT_FLAG	0x12345678



static void __iomem *m10v_smp_base;



static int m10v_boot_secondary(unsigned int l_cpu, struct task_struct *idle)

{

	unsigned int mpidr, cpu, cluster;



	if (!m10v_smp_base)

		return -ENXIO;



	mpidr = cpu_logical_map(l_cpu);

	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);

	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);



	if (cpu >= M10V_MAX_CPU)

		return -EINVAL;



	pr_info("%s: cpu %u l_cpu %u cluster %u\n",

			__func__, cpu, l_cpu, cluster);



	writel(__pa_symbol(secondary_startup), m10v_smp_base + cpu * 4);

	arch_send_wakeup_ipi_mask(cpumask_of(l_cpu));



	return 0;

}



static void m10v_smp_init(unsigned int max_cpus)

{

	unsigned int mpidr, cpu, cluster;

	struct device_node *np;



	np = of_find_compatible_node(NULL, NULL, "socionext,milbeaut-smp-sram");

	if (!np)

		return;



	m10v_smp_base = of_iomap(np, 0);

	if (!m10v_smp_base)

		return;



	mpidr = read_cpuid_mpidr();

	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);

	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);

	pr_info("MCPM boot on cpu_%u cluster_%u\n", cpu, cluster);



	for (cpu = 0; cpu < M10V_MAX_CPU; cpu++)

		writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);

}



static void m10v_cpu_die(unsigned int l_cpu)

{

	gic_cpu_if_down(0);

	v7_exit_coherency_flush(louis);

	wfi();

}



static int m10v_cpu_kill(unsigned int l_cpu)

{

	unsigned int mpidr, cpu;



	mpidr = cpu_logical_map(l_cpu);

	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);



	writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);



	return 1;

}



static struct smp_operations m10v_smp_ops __initdata = {

	.smp_prepare_cpus	= m10v_smp_init,

	.smp_boot_secondary	= m10v_boot_secondary,

	.cpu_die		= m10v_cpu_die,

	.cpu_kill		= m10v_cpu_kill,

};

CPU_METHOD_OF_DECLARE(m10v_smp, "socionext,milbeaut-m10v-smp", &m10v_smp_ops);



static int m10v_pm_valid(suspend_state_t state)

{

	return (state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM);

}



typedef void (*phys_reset_t)(unsigned long);

static phys_reset_t phys_reset;



static int m10v_die(unsigned long arg)

{

	setup_mm_for_reboot();

	asm("wfi");

	/* Boot just like a secondary */

	phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);

	phys_reset(virt_to_phys(cpu_resume));



	return 0;

}



static int m10v_pm_enter(suspend_state_t state)

{

	switch (state) {

	case PM_SUSPEND_STANDBY:

		asm("wfi");

		break;

	case PM_SUSPEND_MEM:

		cpu_pm_enter();

		cpu_suspend(0, m10v_die);

		cpu_pm_exit();

		break;

	}

	return 0;

}



static const struct platform_suspend_ops m10v_pm_ops = {

	.valid		= m10v_pm_valid,

	.enter		= m10v_pm_enter,

};



struct clk *m10v_clclk_register(struct device *cpu_dev);



static int __init m10v_pm_init(void)

{

	if (of_machine_is_compatible("socionext,milbeaut-evb"))

		suspend_set_ops(&m10v_pm_ops);



	return 0;

}

late_initcall(m10v_pm_init);