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Commit 9f730a60 authored by James Hogan's avatar James Hogan Committed by Paolo Bonzini
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MIPS: uasm: Add MTHI/MTLO instructions 



Add MTHI/MTLO instructions for writing to the hi & lo registers to uasm
so that KVM can use uasm for generating its entry point code at runtime.

Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Acked-by: default avatarRalf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 61c64cf9

arch/mips/include/asm/uasm.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -146,6 +146,8 @@ Ip_u1(_mfhi); 
Ip_u1(_mflo);

Ip_u1(_mflo);

Ip_u1u2u3(_mtc0);

Ip_u1u2u3(_mtc0);

Ip_u1u2u3(_mthc0);

Ip_u1u2u3(_mthc0);

Ip_u1(_mthi);

Ip_u1(_mtlo);

Ip_u3u1u2(_mul);

Ip_u3u1u2(_mul);

Ip_u3u1u2(_or);

Ip_u3u1u2(_or);

Ip_u2u1u3(_ori);

Ip_u2u1u3(_ori);

arch/mips/include/uapi/asm/inst.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -375,7 +375,9 @@ enum mm_32axf_minor_op { 
	mm_mflo32_op = 0x075,

	mm_mflo32_op = 0x075,

	mm_jalrhb_op = 0x07c,

	mm_jalrhb_op = 0x07c,

	mm_tlbwi_op = 0x08d,

	mm_tlbwi_op = 0x08d,

	mm_mthi32_op = 0x0b5,

	mm_tlbwr_op = 0x0cd,

	mm_tlbwr_op = 0x0cd,

	mm_mtlo32_op = 0x0f5,

	mm_di_op = 0x11d,

	mm_di_op = 0x11d,

	mm_jalrs_op = 0x13c,

	mm_jalrs_op = 0x13c,

	mm_jalrshb_op = 0x17c,

	mm_jalrshb_op = 0x17c,

arch/mips/mm/uasm-micromips.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -89,6 +89,8 @@ static struct insn insn_table_MM[] = { 
	{ insn_mfhi, M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS },

	{ insn_mfhi, M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS },

	{ insn_mflo, M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS },

	{ insn_mflo, M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS },

	{ insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD },

	{ insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD },

	{ insn_mthi, M(mm_pool32a_op, 0, 0, 0, mm_mthi32_op, mm_pool32axf_op), RS },

	{ insn_mtlo, M(mm_pool32a_op, 0, 0, 0, mm_mtlo32_op, mm_pool32axf_op), RS },

	{ insn_mul, M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD },

	{ insn_mul, M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD },

	{ insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD },

	{ insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD },

	{ insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },

	{ insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },

arch/mips/mm/uasm-mips.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -119,6 +119,8 @@ static struct insn insn_table[] = { 
	{ insn_mflo,  M(spec_op, 0, 0, 0, 0, mflo_op), RD },

	{ insn_mflo,  M(spec_op, 0, 0, 0, 0, mflo_op), RD },

	{ insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},

	{ insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},

	{ insn_mthc0,  M(cop0_op, mthc0_op, 0, 0, 0, 0),  RT | RD | SET},

	{ insn_mthc0,  M(cop0_op, mthc0_op, 0, 0, 0, 0),  RT | RD | SET},

	{ insn_mthi,  M(spec_op, 0, 0, 0, 0, mthi_op), RS },

	{ insn_mtlo,  M(spec_op, 0, 0, 0, 0, mtlo_op), RS },

	{ insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},

	{ insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},

	{ insn_ori,  M(ori_op, 0, 0, 0, 0, 0),	RS | RT | UIMM },

	{ insn_ori,  M(ori_op, 0, 0, 0, 0, 0),	RS | RT | UIMM },

	{ insn_or,  M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD },

	{ insn_or,  M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD },

arch/mips/mm/uasm.c

+8 −5
Original line number Original line Diff line number Diff line
@@ -56,11 +56,12 @@ enum opcode { 
	insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb,

	insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb,

	insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw,

	insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw,

	insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, insn_mflo, insn_mtc0,

	insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, insn_mflo, insn_mtc0,

	insn_mthc0, insn_mul, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr,

	insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_or, insn_ori,

	insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv, insn_slt, insn_sltiu,

	insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll,

	insn_sltu, insn_sra, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync,

	insn_sllv, insn_slt, insn_sltiu, insn_sltu, insn_sra, insn_srl,

	insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait,

	insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp,

	insn_wsbh, insn_xor, insn_xori, insn_yield, insn_lddir, insn_ldpte,

	insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor,

	insn_xori, insn_yield, insn_lddir, insn_ldpte,

};

};





struct insn {

struct insn {
@@ -306,6 +307,8 @@ I_u1(_mfhi) 
I_u1(_mflo)

I_u1(_mflo)

I_u1u2u3(_mtc0)

I_u1u2u3(_mtc0)

I_u1u2u3(_mthc0)

I_u1u2u3(_mthc0)

I_u1(_mthi)

I_u1(_mtlo)

I_u3u1u2(_mul)

I_u3u1u2(_mul)

I_u2u1u3(_ori)

I_u2u1u3(_ori)

I_u3u1u2(_or)

I_u3u1u2(_or)