x86, uv: update macros used by UV platform (9f5314fb) · Commits · e / devices / android_kernel_fairphone_FP5

arch/x86/kernel/genx2apic_uv_x.c

+98 −43

Original line number	Original line	Diff line number	Diff line
	@@ -5,7 +5,7 @@
	*		*
	* SGI UV APIC functions (note: not an Intel compatible APIC)		* SGI UV APIC functions (note: not an Intel compatible APIC)
	*		*
	* Copyright (C) 2007 Silicon Graphics, Inc. All rights reserved.		* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
	*/		*/

	#include <linux/threads.h>		#include <linux/threads.h>
	@@ -55,37 +55,37 @@ static cpumask_t uv_vector_allocation_domain(int cpu)
	int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)		int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
	{		{
	unsigned long val;		unsigned long val;
	int nasid;		int pnode;

	nasid = uv_apicid_to_nasid(phys_apicid);		pnode = uv_apicid_to_pnode(phys_apicid);
	val = (1UL << UVH_IPI_INT_SEND_SHFT) \|		val = (1UL << UVH_IPI_INT_SEND_SHFT) \|
	(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) \|		(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) \|
	(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) \|		(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) \|
	APIC_DM_INIT;		APIC_DM_INIT;
	uv_write_global_mmr64(nasid, UVH_IPI_INT, val);		uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
	mdelay(10);		mdelay(10);

	val = (1UL << UVH_IPI_INT_SEND_SHFT) \|		val = (1UL << UVH_IPI_INT_SEND_SHFT) \|
	(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) \|		(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) \|
	(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) \|		(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) \|
	APIC_DM_STARTUP;		APIC_DM_STARTUP;
	uv_write_global_mmr64(nasid, UVH_IPI_INT, val);		uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
	return 0;		return 0;
	}		}

	static void uv_send_IPI_one(int cpu, int vector)		static void uv_send_IPI_one(int cpu, int vector)
	{		{
	unsigned long val, apicid, lapicid;		unsigned long val, apicid, lapicid;
	int nasid;		int pnode;

	apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */		apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
	lapicid = apicid & 0x3f; /* ZZZ macro needed */		lapicid = apicid & 0x3f; /* ZZZ macro needed */
	nasid = uv_apicid_to_nasid(apicid);		pnode = uv_apicid_to_pnode(apicid);
	val =		val =
	(1UL << UVH_IPI_INT_SEND_SHFT) \| (lapicid <<		(1UL << UVH_IPI_INT_SEND_SHFT) \| (lapicid <<
	UVH_IPI_INT_APIC_ID_SHFT) \|		UVH_IPI_INT_APIC_ID_SHFT) \|
	(vector << UVH_IPI_INT_VECTOR_SHFT);		(vector << UVH_IPI_INT_VECTOR_SHFT);
	uv_write_global_mmr64(nasid, UVH_IPI_INT, val);		uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
	}		}

	static void uv_send_IPI_mask(cpumask_t mask, int vector)		static void uv_send_IPI_mask(cpumask_t mask, int vector)
	@@ -159,39 +159,81 @@ struct genapic apic_x2apic_uv_x = {
	.phys_pkg_id = phys_pkg_id, /* Fixme ZZZ */		.phys_pkg_id = phys_pkg_id, /* Fixme ZZZ */
	};		};

	static __cpuinit void set_x2apic_extra_bits(int nasid)		static __cpuinit void set_x2apic_extra_bits(int pnode)
	{		{
	__get_cpu_var(x2apic_extra_bits) = ((nasid >> 1) << 6);		__get_cpu_var(x2apic_extra_bits) = (pnode << 6);
	}		}

	/*		/*
	* Called on boot cpu.		* Called on boot cpu.
	*/		*/
			static __init int boot_pnode_to_blade(int pnode)
			{
			int blade;

			for (blade = 0; blade < uv_num_possible_blades(); blade++)
			if (pnode == uv_blade_info[blade].pnode)
			return blade;
			BUG();
			}

			struct redir_addr {
			unsigned long redirect;
			unsigned long alias;
			};

			#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT

			static __initdata struct redir_addr redir_addrs[] = {
			{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
			{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
			{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
			};

			static __init void get_lowmem_redirect(unsigned long base, unsigned long size)
			{
			union uvh_si_alias0_overlay_config_u alias;
			union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
			int i;

			for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
			alias.v = uv_read_local_mmr(redir_addrs[i].alias);
			if (alias.s.base == 0) {
			*size = (1UL << alias.s.m_alias);
			redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
			*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
			return;
			}
			}
			BUG();
			}

	static __init void uv_system_init(void)		static __init void uv_system_init(void)
	{		{
	union uvh_si_addr_map_config_u m_n_config;		union uvh_si_addr_map_config_u m_n_config;
	int bytes, nid, cpu, lcpu, nasid, last_nasid, blade;		union uvh_node_id_u node_id;
	unsigned long mmr_base;		unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
			int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
			unsigned long mmr_base, present;

	m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);		m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
			m_val = m_n_config.s.m_skt;
			n_val = m_n_config.s.n_skt;
	mmr_base =		mmr_base =
	uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &		uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
	~UV_MMR_ENABLE;		~UV_MMR_ENABLE;
	printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);		printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);

	last_nasid = -1;		for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
	for_each_possible_cpu(cpu) {		uv_possible_blades +=
	nid = cpu_to_node(cpu);		hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
	nasid = uv_apicid_to_nasid(per_cpu(x86_cpu_to_apicid, cpu));
	if (nasid != last_nasid)
	uv_possible_blades++;
	last_nasid = nasid;
	}
	printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());		printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());

	bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();		bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
	uv_blade_info = alloc_bootmem_pages(bytes);		uv_blade_info = alloc_bootmem_pages(bytes);

			get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);

	bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();		bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
	uv_node_to_blade = alloc_bootmem_pages(bytes);		uv_node_to_blade = alloc_bootmem_pages(bytes);
	memset(uv_node_to_blade, 255, bytes);		memset(uv_node_to_blade, 255, bytes);
	@@ -200,43 +242,56 @@ static __init void uv_system_init(void)
	uv_cpu_to_blade = alloc_bootmem_pages(bytes);		uv_cpu_to_blade = alloc_bootmem_pages(bytes);
	memset(uv_cpu_to_blade, 255, bytes);		memset(uv_cpu_to_blade, 255, bytes);

	last_nasid = -1;		blade = 0;
	blade = -1;		for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
	lcpu = -1;		present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
	for_each_possible_cpu(cpu) {		for (j = 0; j < 64; j++) {
	nid = cpu_to_node(cpu);		if (!test_bit(j, &present))
	nasid = uv_apicid_to_nasid(per_cpu(x86_cpu_to_apicid, cpu));		continue;
	if (nasid != last_nasid) {		uv_blade_info[blade].pnode = (i * 64 + j);
	blade++;		uv_blade_info[blade].nr_possible_cpus = 0;
	lcpu = -1;
	uv_blade_info[blade].nr_posible_cpus = 0;
	uv_blade_info[blade].nr_online_cpus = 0;		uv_blade_info[blade].nr_online_cpus = 0;
			blade++;
			}
	}		}
	last_nasid = nasid;
	lcpu++;

	uv_cpu_hub_info(cpu)->m_val = m_n_config.s.m_skt;		node_id.v = uv_read_local_mmr(UVH_NODE_ID);
	uv_cpu_hub_info(cpu)->n_val = m_n_config.s.n_skt;		gnode_upper = (((unsigned long)node_id.s.node_id) &
			~((1 << n_val) - 1)) << m_val;

			for_each_present_cpu(cpu) {
			nid = cpu_to_node(cpu);
			pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
			blade = boot_pnode_to_blade(pnode);
			lcpu = uv_blade_info[blade].nr_possible_cpus;
			uv_blade_info[blade].nr_possible_cpus++;

			uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
			uv_cpu_hub_info(cpu)->lowmem_remap_top =
			lowmem_redir_base + lowmem_redir_size;
			uv_cpu_hub_info(cpu)->m_val = m_val;
			uv_cpu_hub_info(cpu)->n_val = m_val;
	uv_cpu_hub_info(cpu)->numa_blade_id = blade;		uv_cpu_hub_info(cpu)->numa_blade_id = blade;
	uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;		uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
	uv_cpu_hub_info(cpu)->local_nasid = nasid;		uv_cpu_hub_info(cpu)->pnode = pnode;
	uv_cpu_hub_info(cpu)->gnode_upper =		uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
	nasid & ~((1 << uv_hub_info->n_val) - 1);		uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
			uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
	uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;		uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
	uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */		uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
	uv_blade_info[blade].nasid = nasid;
	uv_blade_info[blade].nr_posible_cpus++;
	uv_node_to_blade[nid] = blade;		uv_node_to_blade[nid] = blade;
	uv_cpu_to_blade[cpu] = blade;		uv_cpu_to_blade[cpu] = blade;

	printk(KERN_DEBUG "UV cpu %d, apicid 0x%x, nasid %d, nid %d\n",		printk(KERN_DEBUG "UV cpu %d, apicid 0x%x, pnode %d, nid %d, "
	cpu, per_cpu(x86_cpu_to_apicid, cpu), nasid, nid);		"lcpu %d, blade %d\n",
	printk(KERN_DEBUG "UV lcpu %d, blade %d\n", lcpu, blade);		cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
			lcpu, blade);
	}		}
	}		}

	/*		/*
	* Called on each cpu to initialize the per_cpu UV data area.		* Called on each cpu to initialize the per_cpu UV data area.
			* ZZZ hotplug not supported yet
	*/		*/
	void __cpuinit uv_cpu_init(void)		void __cpuinit uv_cpu_init(void)
	{		{
	@@ -246,5 +301,5 @@ void __cpuinit uv_cpu_init(void)
	uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;		uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;

	if (get_uv_system_type() == UV_NON_UNIQUE_APIC)		if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
	set_x2apic_extra_bits(uv_hub_info->local_nasid);		set_x2apic_extra_bits(uv_hub_info->pnode);
	}		}

include/asm-x86/uv/uv_hub.h

+128 −60

Original line number	Original line	Diff line number	Diff line
	@@ -5,7 +5,7 @@
	*		*
	* SGI UV architectural definitions		* SGI UV architectural definitions
	*		*
	* Copyright (C) 2007 Silicon Graphics, Inc. All rights reserved.		* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
	*/		*/

	#ifndef __ASM_X86_UV_HUB_H__		#ifndef __ASM_X86_UV_HUB_H__
	@@ -20,26 +20,49 @@
	/*		/*
	* Addressing Terminology		* Addressing Terminology
	*		*
			* M - The low M bits of a physical address represent the offset
			* into the blade local memory. RAM memory on a blade is physically
			* contiguous (although various IO spaces may punch holes in
			* it)..
			*
			* N - Number of bits in the node portion of a socket physical
			* address.
			*
	* NASID - network ID of a router, Mbrick or Cbrick. Nasid values of		* NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
	* routers always have low bit of 1, C/MBricks have low bit		* routers always have low bit of 1, C/MBricks have low bit
	* equal to 0. Most addressing macros that target UV hub chips		* equal to 0. Most addressing macros that target UV hub chips
	* right shift the NASID by 1 to exclude the always-zero bit.		* right shift the NASID by 1 to exclude the always-zero bit.
			* NASIDs contain up to 15 bits.
			*
			* GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
			* of nasids.
			*
			* PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
			* of the nasid for socket usage.
	*		*
	* SNASID - NASID right shifted by 1 bit.		*
			* NumaLink Global Physical Address Format:
			* +--------------------------------+---------------------+
			* \|00..000\| GNODE \| NodeOffset \|
			* +--------------------------------+---------------------+
			* \|<-------53 - M bits --->\|<--------M bits ----->
			*
			* M - number of node offset bits (35 .. 40)
	*		*
	*		*
	* Memory/UV-HUB Processor Socket Address Format:		* Memory/UV-HUB Processor Socket Address Format:
	* +--------+---------------+---------------------+		* +----------------+---------------+---------------------+
	* \|00..0000\| SNASID \| NodeOffset \|		* \|00..000000000000\| PNODE \| NodeOffset \|
	* +--------+---------------+---------------------+		* +----------------+---------------+---------------------+
	* <--- N bits --->\|<--------M bits ----->		* <--- N bits --->\|<--------M bits ----->
	*		*
	* M number of node offset bits (35 .. 40)		* M - number of node offset bits (35 .. 40)
	* N number of SNASID bits (0 .. 10)		* N - number of PNODE bits (0 .. 10)
	*		*
	* Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).		* Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
	* The actual values are configuration dependent and are set at		* The actual values are configuration dependent and are set at
	* boot time		* boot time. M & N values are set by the hardware/BIOS at boot.
			*
	*		*
	* APICID format		* APICID format
	* NOTE!!!!!! This is the current format of the APICID. However, code		* NOTE!!!!!! This is the current format of the APICID. However, code
	@@ -48,14 +71,14 @@
	*		*
	* 1111110000000000		* 1111110000000000
	* 5432109876543210		* 5432109876543210
	* nnnnnnnnnnlc0cch		* pppppppppplc0cch
	* sssssssssss		* sssssssssss
	*		*
	* n = snasid bits		* p = pnode bits
	* l = socket number on board		* l = socket number on board
	* c = core		* c = core
	* h = hyperthread		* h = hyperthread
	* s = bits that are in the socket CSR		* s = bits that are in the SOCKET_ID CSR
	*		*
	* Note: Processor only supports 12 bits in the APICID register. The ACPI		* Note: Processor only supports 12 bits in the APICID register. The ACPI
	* tables hold all 16 bits. Software needs to be aware of this.		* tables hold all 16 bits. Software needs to be aware of this.
	@@ -74,7 +97,7 @@
	* This value is also the value of the maximum number of non-router NASIDs		* This value is also the value of the maximum number of non-router NASIDs
	* in the numalink fabric.		* in the numalink fabric.
	*		*
	* NOTE: a brick may be 1 or 2 OS nodes. Don't get these confused.		* NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
	*/		*/
	#define UV_MAX_NUMALINK_BLADES 16384		#define UV_MAX_NUMALINK_BLADES 16384

	@@ -96,8 +119,12 @@
	*/		*/
	struct uv_hub_info_s {		struct uv_hub_info_s {
	unsigned long global_mmr_base;		unsigned long global_mmr_base;
	unsigned short local_nasid;		unsigned long gpa_mask;
	unsigned short gnode_upper;		unsigned long gnode_upper;
			unsigned long lowmem_remap_top;
			unsigned long lowmem_remap_base;
			unsigned short pnode;
			unsigned short pnode_mask;
	unsigned short coherency_domain_number;		unsigned short coherency_domain_number;
	unsigned short numa_blade_id;		unsigned short numa_blade_id;
	unsigned char blade_processor_id;		unsigned char blade_processor_id;
	@@ -112,83 +139,124 @@ DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
	* Local & Global MMR space macros.		* Local & Global MMR space macros.
	* Note: macros are intended to be used ONLY by inline functions		* Note: macros are intended to be used ONLY by inline functions
	* in this file - not by other kernel code.		* in this file - not by other kernel code.
			* n - NASID (full 15-bit global nasid)
			* g - GNODE (full 15-bit global nasid, right shifted 1)
			* p - PNODE (local part of nsids, right shifted 1)
	*/		*/
	#define UV_SNASID(n) ((n) >> 1)		#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
	#define UV_NASID(n) ((n) << 1)		#define UV_PNODE_TO_NASID(p) (((p) << 1) \| uv_hub_info->gnode_upper)

	#define UV_LOCAL_MMR_BASE 0xf4000000UL		#define UV_LOCAL_MMR_BASE 0xf4000000UL
	#define UV_GLOBAL_MMR32_BASE 0xf8000000UL		#define UV_GLOBAL_MMR32_BASE 0xf8000000UL
	#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)		#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)

	#define UV_GLOBAL_MMR32_SNASID_MASK 0x3ff		#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
	#define UV_GLOBAL_MMR32_SNASID_SHIFT 15		#define UV_GLOBAL_MMR64_PNODE_SHIFT 26
	#define UV_GLOBAL_MMR64_SNASID_SHIFT 26

	#define UV_GLOBAL_MMR32_NASID_BITS(n) \		#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
	(((UV_SNASID(n) & UV_GLOBAL_MMR32_SNASID_MASK)) << \
	(UV_GLOBAL_MMR32_SNASID_SHIFT))

	#define UV_GLOBAL_MMR64_NASID_BITS(n) \		#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
	((unsigned long)UV_SNASID(n) << UV_GLOBAL_MMR64_SNASID_SHIFT)		((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)

			#define UV_APIC_PNODE_SHIFT 6

			/*
			* Macros for converting between kernel virtual addresses, socket local physical
			* addresses, and UV global physical addresses.
			* Note: use the standard __pa() & __va() macros for converting
			* between socket virtual and socket physical addresses.
			*/

			/* socket phys RAM --> UV global physical address */
			static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
			{
			if (paddr < uv_hub_info->lowmem_remap_top)
			paddr += uv_hub_info->lowmem_remap_base;
			return paddr \| uv_hub_info->gnode_upper;
			}


			/* socket virtual --> UV global physical address */
			static inline unsigned long uv_gpa(void *v)
			{
			return __pa(v) \| uv_hub_info->gnode_upper;
			}

			/* socket virtual --> UV global physical address */
			static inline void uv_vgpa(void v)
			{
			return (void *)uv_gpa(v);
			}

			/* UV global physical address --> socket virtual */
			static inline void *uv_va(unsigned long gpa)
			{
			return __va(gpa & uv_hub_info->gpa_mask);
			}

			/* pnode, offset --> socket virtual */
			static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
			{
			return __va(((unsigned long)pnode << uv_hub_info->m_val) \| offset);
			}

	#define UV_APIC_NASID_SHIFT 6

	/*		/*
	* Extract a NASID from an APICID (full apicid, not processor subset)		* Extract a PNODE from an APICID (full apicid, not processor subset)
	*/		*/
	static inline int uv_apicid_to_nasid(int apicid)		static inline int uv_apicid_to_pnode(int apicid)
	{		{
	return (UV_NASID(apicid >> UV_APIC_NASID_SHIFT));		return (apicid >> UV_APIC_PNODE_SHIFT);
	}		}

	/*		/*
	* Access global MMRs using the low memory MMR32 space. This region supports		* Access global MMRs using the low memory MMR32 space. This region supports
	* faster MMR access but not all MMRs are accessible in this space.		* faster MMR access but not all MMRs are accessible in this space.
	*/		*/
	static inline unsigned long *uv_global_mmr32_address(int nasid,		static inline unsigned long *uv_global_mmr32_address(int pnode,
	unsigned long offset)		unsigned long offset)
	{		{
	return __va(UV_GLOBAL_MMR32_BASE \|		return __va(UV_GLOBAL_MMR32_BASE \|
	UV_GLOBAL_MMR32_NASID_BITS(nasid) \| offset);		UV_GLOBAL_MMR32_PNODE_BITS(pnode) \| offset);
	}		}

	static inline void uv_write_global_mmr32(int nasid, unsigned long offset,		static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
	unsigned long val)		unsigned long val)
	{		{
	*uv_global_mmr32_address(nasid, offset) = val;		*uv_global_mmr32_address(pnode, offset) = val;
	}		}

	static inline unsigned long uv_read_global_mmr32(int nasid,		static inline unsigned long uv_read_global_mmr32(int pnode,
	unsigned long offset)		unsigned long offset)
	{		{
	return *uv_global_mmr32_address(nasid, offset);		return *uv_global_mmr32_address(pnode, offset);
	}		}

	/*		/*
	* Access Global MMR space using the MMR space located at the top of physical		* Access Global MMR space using the MMR space located at the top of physical
	* memory.		* memory.
	*/		*/
	static inline unsigned long *uv_global_mmr64_address(int nasid,		static inline unsigned long *uv_global_mmr64_address(int pnode,
	unsigned long offset)		unsigned long offset)
	{		{
	return __va(UV_GLOBAL_MMR64_BASE \|		return __va(UV_GLOBAL_MMR64_BASE \|
	UV_GLOBAL_MMR64_NASID_BITS(nasid) \| offset);		UV_GLOBAL_MMR64_PNODE_BITS(pnode) \| offset);
	}		}

	static inline void uv_write_global_mmr64(int nasid, unsigned long offset,		static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
	unsigned long val)		unsigned long val)
	{		{
	*uv_global_mmr64_address(nasid, offset) = val;		*uv_global_mmr64_address(pnode, offset) = val;
	}		}

	static inline unsigned long uv_read_global_mmr64(int nasid,		static inline unsigned long uv_read_global_mmr64(int pnode,
	unsigned long offset)		unsigned long offset)
	{		{
	return *uv_global_mmr64_address(nasid, offset);		return *uv_global_mmr64_address(pnode, offset);
	}		}

	/*		/*
	* Access node local MMRs. Faster than using global space but only local MMRs		* Access hub local MMRs. Faster than using global space but only local MMRs
	* are accessible.		* are accessible.
	*/		*/
	static inline unsigned long *uv_local_mmr_address(unsigned long offset)		static inline unsigned long *uv_local_mmr_address(unsigned long offset)
	@@ -207,15 +275,15 @@ static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
	}		}

	/*		/*
	* Structures and definitions for converting between cpu, node, and blade		* Structures and definitions for converting between cpu, node, pnode, and blade
	* numbers.		* numbers.
	*/		*/
	struct uv_blade_info {		struct uv_blade_info {
	unsigned short nr_posible_cpus;		unsigned short nr_possible_cpus;
	unsigned short nr_online_cpus;		unsigned short nr_online_cpus;
	unsigned short nasid;		unsigned short pnode;
	};		};
	struct uv_blade_info *uv_blade_info;		extern struct uv_blade_info *uv_blade_info;
	extern short *uv_node_to_blade;		extern short *uv_node_to_blade;
	extern short *uv_cpu_to_blade;		extern short *uv_cpu_to_blade;
	extern short uv_possible_blades;		extern short uv_possible_blades;
	@@ -244,16 +312,16 @@ static inline int uv_node_to_blade_id(int nid)
	return uv_node_to_blade[nid];		return uv_node_to_blade[nid];
	}		}

	/* Convert a blade id to the NASID of the blade */		/* Convert a blade id to the PNODE of the blade */
	static inline int uv_blade_to_nasid(int bid)		static inline int uv_blade_to_pnode(int bid)
	{		{
	return uv_blade_info[bid].nasid;		return uv_blade_info[bid].pnode;
	}		}

	/* Determine the number of possible cpus on a blade */		/* Determine the number of possible cpus on a blade */
	static inline int uv_blade_nr_possible_cpus(int bid)		static inline int uv_blade_nr_possible_cpus(int bid)
	{		{
	return uv_blade_info[bid].nr_posible_cpus;		return uv_blade_info[bid].nr_possible_cpus;
	}		}

	/* Determine the number of online cpus on a blade */		/* Determine the number of online cpus on a blade */
	@@ -262,16 +330,16 @@ static inline int uv_blade_nr_online_cpus(int bid)
	return uv_blade_info[bid].nr_online_cpus;		return uv_blade_info[bid].nr_online_cpus;
	}		}

	/* Convert a cpu id to the NASID of the blade containing the cpu */		/* Convert a cpu id to the PNODE of the blade containing the cpu */
	static inline int uv_cpu_to_nasid(int cpu)		static inline int uv_cpu_to_pnode(int cpu)
	{		{
	return uv_blade_info[uv_cpu_to_blade_id(cpu)].nasid;		return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
	}		}

	/* Convert a node number to the NASID of the blade */		/* Convert a linux node number to the PNODE of the blade */
	static inline int uv_node_to_nasid(int nid)		static inline int uv_node_to_pnode(int nid)
	{		{
	return uv_blade_info[uv_node_to_blade_id(nid)].nasid;		return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
	}		}

	/* Maximum possible number of blades */		/* Maximum possible number of blades */

include/asm-x86/uv/uv_mmrs.h

+505 −4

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