drm/radeon/kms: convert r4xx to new init path (9f022ddf) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/gpu/drm/radeon/r100.c

+108 −6

Original line number	Diff line number	Diff line
		@@ -299,6 +299,17 @@ int r100_irq_set(struct radeon_device *rdev)
		return 0;
		}

		void r100_irq_disable(struct radeon_device *rdev)
		{
		u32 tmp;

		WREG32(R_000040_GEN_INT_CNTL, 0);
		/* Wait and acknowledge irq */
		mdelay(1);
		tmp = RREG32(R_000044_GEN_INT_STATUS);
		WREG32(R_000044_GEN_INT_STATUS, tmp);
		}

		static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
		{
		uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
		@@ -396,14 +407,21 @@ int r100_wb_init(struct radeon_device *rdev)
		return r;
		}
		}
		WREG32(RADEON_SCRATCH_ADDR, rdev->wb.gpu_addr);
		WREG32(RADEON_CP_RB_RPTR_ADDR, rdev->wb.gpu_addr + 1024);
		WREG32(RADEON_SCRATCH_UMSK, 0xff);
		WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
		WREG32(R_00070C_CP_RB_RPTR_ADDR,
		S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
		WREG32(R_000770_SCRATCH_UMSK, 0xff);
		return 0;
		}

		void r100_wb_disable(struct radeon_device *rdev)
		{
		WREG32(R_000770_SCRATCH_UMSK, 0);
		}

		void r100_wb_fini(struct radeon_device *rdev)
		{
		r100_wb_disable(rdev);
		if (rdev->wb.wb_obj) {
		radeon_object_kunmap(rdev->wb.wb_obj);
		radeon_object_unpin(rdev->wb.wb_obj);
		@@ -1581,11 +1599,12 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
		int r100_cs_parse(struct radeon_cs_parser *p)
		{
		struct radeon_cs_packet pkt;
		struct r100_cs_track track;
		struct r100_cs_track *track;
		int r;

		r100_cs_track_clear(p->rdev, &track);
		p->track = &track;
		track = kzalloc(sizeof(*track), GFP_KERNEL);
		r100_cs_track_clear(p->rdev, track);
		p->track = track;
		do {
		r = r100_cs_packet_parse(p, &pkt, p->idx);
		if (r) {
		@@ -3085,3 +3104,86 @@ int r100_ib_test(struct radeon_device *rdev)
		radeon_ib_free(rdev, &ib);
		return r;
		}

		void r100_ib_fini(struct radeon_device *rdev)
		{
		radeon_ib_pool_fini(rdev);
		}

		int r100_ib_init(struct radeon_device *rdev)
		{
		int r;

		r = radeon_ib_pool_init(rdev);
		if (r) {
		dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
		r100_ib_fini(rdev);
		return r;
		}
		r = r100_ib_test(rdev);
		if (r) {
		dev_err(rdev->dev, "failled testing IB (%d).\n", r);
		r100_ib_fini(rdev);
		return r;
		}
		return 0;
		}

		void r100_mc_stop(struct radeon_device rdev, struct r100_mc_save save)
		{
		/* Shutdown CP we shouldn't need to do that but better be safe than
		* sorry
		*/
		rdev->cp.ready = false;
		WREG32(R_000740_CP_CSQ_CNTL, 0);

		/* Save few CRTC registers */
		save->GENMO_WT = RREG32(R_0003C0_GENMO_WT);
		save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
		save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
		save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
		if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
		save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
		}

		/* Disable VGA aperture access */
		WREG32(R_0003C0_GENMO_WT, C_0003C0_VGA_RAM_EN & save->GENMO_WT);
		/* Disable cursor, overlay, crtc */
		WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET \| S_000260_CUR_LOCK(1));
		WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL \|
		S_000054_CRTC_DISPLAY_DIS(1));
		WREG32(R_000050_CRTC_GEN_CNTL,
		(C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) \|
		S_000050_CRTC_DISP_REQ_EN_B(1));
		WREG32(R_000420_OV0_SCALE_CNTL,
		C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
		WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
		if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET \|
		S_000360_CUR2_LOCK(1));
		WREG32(R_0003F8_CRTC2_GEN_CNTL,
		(C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) \|
		S_0003F8_CRTC2_DISPLAY_DIS(1) \|
		S_0003F8_CRTC2_DISP_REQ_EN_B(1));
		WREG32(R_000360_CUR2_OFFSET,
		C_000360_CUR2_LOCK & save->CUR2_OFFSET);
		}
		}

		void r100_mc_resume(struct radeon_device rdev, struct r100_mc_save save)
		{
		/* Update base address for crtc */
		WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
		if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
		rdev->mc.vram_location);
		}
		/* Restore CRTC registers */
		WREG32(R_0003C0_GENMO_WT, save->GENMO_WT);
		WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
		WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
		if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
		}
		}

drivers/gpu/drm/radeon/r100d.h

+471 −0

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/radeon/r300.c

+46 −4

Original line number	Diff line number	Diff line
		@@ -1241,11 +1241,12 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
		int r300_cs_parse(struct radeon_cs_parser *p)
		{
		struct radeon_cs_packet pkt;
		struct r100_cs_track track;
		struct r100_cs_track *track;
		int r;

		r100_cs_track_clear(p->rdev, &track);
		p->track = &track;
		track = kzalloc(sizeof(*track), GFP_KERNEL);
		r100_cs_track_clear(p->rdev, track);
		p->track = track;
		do {
		r = r100_cs_packet_parse(p, &pkt, p->idx);
		if (r) {
		@@ -1275,9 +1276,50 @@ int r300_cs_parse(struct radeon_cs_parser *p)
		return 0;
		}

		int r300_init(struct radeon_device *rdev)
		void r300_set_reg_safe(struct radeon_device *rdev)
		{
		rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
		rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
		}

		int r300_init(struct radeon_device *rdev)
		{
		r300_set_reg_safe(rdev);
		return 0;
		}

		void r300_mc_program(struct radeon_device *rdev)
		{
		struct r100_mc_save save;
		int r;

		r = r100_debugfs_mc_info_init(rdev);
		if (r) {
		dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		}

		/* Stops all mc clients */
		r100_mc_stop(rdev, &save);
		/* Shutdown PCI/PCIE GART */
		radeon_gart_disable(rdev);
		if (rdev->flags & RADEON_IS_AGP) {
		WREG32(R_00014C_MC_AGP_LOCATION,
		S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		WREG32(R_00015C_AGP_BASE_2,
		upper_32_bits(rdev->mc.agp_base) & 0xff);
		} else {
		WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		WREG32(R_000170_AGP_BASE, 0);
		WREG32(R_00015C_AGP_BASE_2, 0);
		}
		/* Wait for mc idle */
		if (r300_mc_wait_for_idle(rdev))
		DRM_INFO("Failed to wait MC idle before programming MC.\n");
		/* Program MC, should be a 32bits limited address space */
		WREG32(R_000148_MC_FB_LOCATION,
		S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		r100_mc_resume(rdev, &save);
		}

drivers/gpu/drm/radeon/r300d.h

+25 −0

Original line number	Diff line number	Diff line
		@@ -73,4 +73,29 @@
		#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
		#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)

		/* Registers */
		#define R_000148_MC_FB_LOCATION 0x000148
		#define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0)
		#define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
		#define C_000148_MC_FB_START 0xFFFF0000
		#define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
		#define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
		#define C_000148_MC_FB_TOP 0x0000FFFF
		#define R_00014C_MC_AGP_LOCATION 0x00014C
		#define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0)
		#define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF)
		#define C_00014C_MC_AGP_START 0xFFFF0000
		#define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16)
		#define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF)
		#define C_00014C_MC_AGP_TOP 0x0000FFFF
		#define R_00015C_AGP_BASE_2 0x00015C
		#define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0)
		#define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF)
		#define C_00015C_AGP_BASE_ADDR_2 0xFFFFFFF0
		#define R_000170_AGP_BASE 0x000170
		#define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
		#define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
		#define C_000170_AGP_BASE_ADDR 0x00000000


		#endif

drivers/gpu/drm/radeon/r420.c

+202 −91

Original line number	Diff line number	Diff line
		@@ -29,48 +29,13 @@
		#include "drmP.h"
		#include "radeon_reg.h"
		#include "radeon.h"
		#include "atom.h"
		#include "r420d.h"

		/* r420,r423,rv410 depends on : */
		void r100_pci_gart_disable(struct radeon_device *rdev);
		void r100_hdp_reset(struct radeon_device *rdev);
		void r100_mc_setup(struct radeon_device *rdev);
		int r100_gui_wait_for_idle(struct radeon_device *rdev);
		void r100_mc_disable_clients(struct radeon_device *rdev);
		void r300_vram_info(struct radeon_device *rdev);
		int r300_mc_wait_for_idle(struct radeon_device *rdev);
		int rv370_pcie_gart_enable(struct radeon_device *rdev);
		void rv370_pcie_gart_disable(struct radeon_device *rdev);

		/* This files gather functions specifics to :
		* r420,r423,rv410
		*
		* Some of these functions might be used by newer ASICs.
		*/
		void r420_gpu_init(struct radeon_device *rdev);
		int r420_debugfs_pipes_info_init(struct radeon_device *rdev);


		/*
		* MC
		*/
		int r420_mc_init(struct radeon_device *rdev)
		{
		int r;

		if (r100_debugfs_rbbm_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
		}
		if (r420_debugfs_pipes_info_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for pipes !\n");
		}

		r420_gpu_init(rdev);
		r100_pci_gart_disable(rdev);
		if (rdev->flags & RADEON_IS_PCIE) {
		rv370_pcie_gart_disable(rdev);
		}

		/* Setup GPU memory space */
		rdev->mc.vram_location = 0xFFFFFFFFUL;
		rdev->mc.gtt_location = 0xFFFFFFFFUL;
		@@ -88,38 +53,9 @@ int r420_mc_init(struct radeon_device *rdev)
		if (r) {
		return r;
		}

		/* Program GPU memory space */
		r100_mc_disable_clients(rdev);
		if (r300_mc_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait MC idle while "
		"programming pipes. Bad things might happen.\n");
		}
		r100_mc_setup(rdev);
		return 0;
		}

		void r420_mc_fini(struct radeon_device *rdev)
		{
		if (rdev->flags & RADEON_IS_PCIE) {
		rv370_pcie_gart_disable(rdev);
		radeon_gart_table_vram_free(rdev);
		} else {
		r100_pci_gart_disable(rdev);
		radeon_gart_table_ram_free(rdev);
		}
		radeon_gart_fini(rdev);
		}


		/*
		* Global GPU functions
		*/
		void r420_errata(struct radeon_device *rdev)
		{
		rdev->pll_errata = 0;
		}

		void r420_pipes_init(struct radeon_device *rdev)
		{
		unsigned tmp;
		@@ -185,25 +121,216 @@ void r420_pipes_init(struct radeon_device *rdev)
		rdev->num_gb_pipes, rdev->num_z_pipes);
		}

		void r420_gpu_init(struct radeon_device *rdev)
		u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
		{
		r100_hdp_reset(rdev);
		u32 r;

		WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
		r = RREG32(R_0001FC_MC_IND_DATA);
		return r;
		}

		void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		{
		WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) \|
		S_0001F8_MC_IND_WR_EN(1));
		WREG32(R_0001FC_MC_IND_DATA, v);
		}

		static void r420_debugfs(struct radeon_device *rdev)
		{
		if (r100_debugfs_rbbm_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
		}
		if (r420_debugfs_pipes_info_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for pipes !\n");
		}
		}

		static void r420_clock_resume(struct radeon_device *rdev)
		{
		u32 sclk_cntl;
		sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
		sclk_cntl \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		if (rdev->family == CHIP_R420)
		sclk_cntl \|= S_00000D_FORCE_PX(1) \| S_00000D_FORCE_TX(1);
		WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
		}

		int r420_resume(struct radeon_device *rdev)
		{
		int r;

		/* Resume clock before doing reset */
		r420_clock_resume(rdev);
		/* Reset gpu before posting otherwise ATOM will enter infinite loop */
		if (radeon_gpu_reset(rdev)) {
		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		RREG32(R_000E40_RBBM_STATUS),
		RREG32(R_0007C0_CP_STAT));
		}
		/* check if cards are posted or not */
		if (rdev->is_atom_bios) {
		atom_asic_init(rdev->mode_info.atom_context);
		} else {
		radeon_combios_asic_init(rdev->ddev);
		}
		/* Resume clock after posting */
		r420_clock_resume(rdev);
		r300_mc_program(rdev);
		/* Initialize GART (initialize after TTM so we can allocate
		* memory through TTM but finalize after TTM) */
		r = radeon_gart_enable(rdev);
		if (r) {
		dev_err(rdev->dev, "failled initializing GART (%d).\n", r);
		return r;
		}
		r420_pipes_init(rdev);
		if (r300_mc_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait MC idle while "
		"programming pipes. Bad things might happen.\n");
		/* Enable IRQ */
		rdev->irq.sw_int = true;
		r100_irq_set(rdev);
		/* 1M ring buffer */
		r = r100_cp_init(rdev, 1024 * 1024);
		if (r) {
		dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
		return r;
		}
		r = r100_wb_init(rdev);
		if (r) {
		dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
		}
		r = r100_ib_init(rdev);
		if (r) {
		dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
		return r;
		}
		return 0;
		}

		int r420_suspend(struct radeon_device *rdev)
		{
		r100_cp_disable(rdev);
		r100_wb_disable(rdev);
		r100_irq_disable(rdev);
		radeon_gart_disable(rdev);
		return 0;
		}

		/*
		* r420,r423,rv410 VRAM info
		*/
		void r420_vram_info(struct radeon_device *rdev)
		void r420_fini(struct radeon_device *rdev)
		{
		r300_vram_info(rdev);
		r100_cp_fini(rdev);
		r100_wb_fini(rdev);
		r100_ib_fini(rdev);
		radeon_gem_fini(rdev);
		if (rdev->flags & RADEON_IS_PCIE) {
		rv370_pcie_gart_disable(rdev);
		radeon_gart_table_vram_free(rdev);
		} else {
		r100_pci_gart_disable(rdev);
		radeon_gart_table_ram_free(rdev);
		}
		radeon_gart_fini(rdev);
		radeon_agp_fini(rdev);
		radeon_irq_kms_fini(rdev);
		radeon_fence_driver_fini(rdev);
		radeon_object_fini(rdev);
		if (rdev->is_atom_bios) {
		radeon_atombios_fini(rdev);
		} else {
		radeon_combios_fini(rdev);
		}
		kfree(rdev->bios);
		rdev->bios = NULL;
		}

		int r420_init(struct radeon_device *rdev)
		{
		int r;

		rdev->new_init_path = true;
		/* Initialize scratch registers */
		radeon_scratch_init(rdev);
		/* Initialize surface registers */
		radeon_surface_init(rdev);
		/* TODO: disable VGA need to use VGA request */
		/* BIOS*/
		if (!radeon_get_bios(rdev)) {
		if (ASIC_IS_AVIVO(rdev))
		return -EINVAL;
		}
		if (rdev->is_atom_bios) {
		r = radeon_atombios_init(rdev);
		if (r) {
		return r;
		}
		} else {
		r = radeon_combios_init(rdev);
		if (r) {
		return r;
		}
		}
		/* Reset gpu before posting otherwise ATOM will enter infinite loop */
		if (radeon_gpu_reset(rdev)) {
		dev_warn(rdev->dev,
		"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		RREG32(R_000E40_RBBM_STATUS),
		RREG32(R_0007C0_CP_STAT));
		}
		/* check if cards are posted or not */
		if (!radeon_card_posted(rdev) && rdev->bios) {
		DRM_INFO("GPU not posted. posting now...\n");
		if (rdev->is_atom_bios) {
		atom_asic_init(rdev->mode_info.atom_context);
		} else {
		radeon_combios_asic_init(rdev->ddev);
		}
		}
		/* Initialize clocks */
		radeon_get_clock_info(rdev->ddev);
		/* Get vram informations */
		r300_vram_info(rdev);
		/* Initialize memory controller (also test AGP) */
		r = r420_mc_init(rdev);
		if (r) {
		return r;
		}
		r420_debugfs(rdev);
		/* Fence driver */
		r = radeon_fence_driver_init(rdev);
		if (r) {
		return r;
		}
		r = radeon_irq_kms_init(rdev);
		if (r) {
		return r;
		}
		/* Memory manager */
		r = radeon_object_init(rdev);
		if (r) {
		return r;
		}
		r300_set_reg_safe(rdev);
		r = r420_resume(rdev);
		if (r) {
		/* Somethings want wront with the accel init stop accel */
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
		r420_suspend(rdev);
		r100_cp_fini(rdev);
		r100_wb_fini(rdev);
		r100_ib_fini(rdev);
		if (rdev->flags & RADEON_IS_PCIE) {
		rv370_pcie_gart_disable(rdev);
		radeon_gart_table_vram_free(rdev);
		} else {
		r100_pci_gart_disable(rdev);
		radeon_gart_table_ram_free(rdev);
		}
		radeon_gart_fini(rdev);
		radeon_agp_fini(rdev);
		radeon_irq_kms_fini(rdev);
		}
		return 0;
		}

		/*
		* Debugfs info
		@@ -238,19 +365,3 @@ int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
		return 0;
		#endif
		}

		u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
		{
		u32 r;

		WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
		r = RREG32(R_0001FC_MC_IND_DATA);
		return r;
		}

		void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		{
		WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) \|
		S_0001F8_MC_IND_WR_EN(1));
		WREG32(R_0001FC_MC_IND_DATA, v);
		}