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Commit 9efe891d authored by Mateusz Kulikowski's avatar Mateusz Kulikowski Committed by Greg Kroah-Hartman
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staging: rtl8192e: Remove unused defines 



Remove most of unused defines (excluding phyreg/hw registers).

Signed-off-by: default avatarMateusz Kulikowski <mateusz.kulikowski@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 04ed5f3d

drivers/staging/rtl8192e/dot11d.h

+0 −4
Original line number Diff line number Diff line
@@ -79,7 +79,6 @@ static inline void cpMacAddr(unsigned char *des, unsigned char *src) 
#define UPDATE_CIE_SRC(__pIeeeDev, __pTa)		\

	cpMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa)



#define CIE_WATCHDOG_TH 1

#define GET_CIE_WATCHDOG(__pIeeeDev)				\

	 (GET_DOT11D_INFO(__pIeeeDev)->CountryIeWatchdog)

static inline void RESET_CIE_WATCHDOG(struct rtllib_device *__pIeeeDev)
@@ -88,9 +87,6 @@ static inline void RESET_CIE_WATCHDOG(struct rtllib_device *__pIeeeDev) 
}

#define UPDATE_CIE_WATCHDOG(__pIeeeDev) (++GET_CIE_WATCHDOG(__pIeeeDev))



#define IS_DOT11D_STATE_DONE(__pIeeeDev)			\

	(GET_DOT11D_INFO(__pIeeeDev)->State == DOT11D_STATE_DONE)



void dot11d_init(struct rtllib_device *dev);

void Dot11d_Channelmap(u8 channel_plan, struct rtllib_device *ieee);

void Dot11d_Reset(struct rtllib_device *dev);

drivers/staging/rtl8192e/rtl8192e/r8190P_def.h

+0 −46
Original line number Diff line number Diff line
@@ -26,8 +26,6 @@ 
#define		MAX_SILENT_RESET_RX_SLOT_NUM	10



#define RX_MPDU_QUEUE				0

#define RX_CMD_QUEUE				1





enum rtl819x_loopback {

	RTL819X_NO_LOOPBACK = 0,
@@ -36,11 +34,6 @@ enum rtl819x_loopback { 
	RTL819X_CCK_LOOPBACK = 3,

};





#define RESET_DELAY_8185			20



#define RT_IBSS_INT_MASKS (IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER)



#define DESC90_RATE1M				0x00

#define DESC90_RATE2M				0x01

#define DESC90_RATE5_5M				0x02
@@ -74,17 +67,6 @@ enum rtl819x_loopback { 
#define SHORT_SLOT_TIME				9

#define NON_SHORT_SLOT_TIME		20





#define	MAX_LINES_HWCONFIG_TXT			1000

#define MAX_BYTES_LINE_HWCONFIG_TXT		128



#define SW_THREE_WIRE			0

#define HW_THREE_WIRE			2



#define BT_DEMO_BOARD			0

#define BT_QA_BOARD				1

#define BT_FPGA					2



#define	RX_SMOOTH				20



#define QSLT_BK					0x1
@@ -96,25 +78,14 @@ enum rtl819x_loopback { 
#define	QSLT_MGNT				0x12

#define	QSLT_CMD				0x13



#define NUM_OF_FIRMWARE_QUEUE				10

#define NUM_OF_PAGES_IN_FW					0x100

#define NUM_OF_PAGE_IN_FW_QUEUE_BK		0x007

#define NUM_OF_PAGE_IN_FW_QUEUE_BE		0x0aa

#define NUM_OF_PAGE_IN_FW_QUEUE_VI		0x024

#define NUM_OF_PAGE_IN_FW_QUEUE_VO		0x007

#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA		0

#define NUM_OF_PAGE_IN_FW_QUEUE_CMD		0x2

#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT		0x10

#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH		0

#define NUM_OF_PAGE_IN_FW_QUEUE_BCN		0x4

#define NUM_OF_PAGE_IN_FW_QUEUE_PUB		0xd



#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM	0x026

#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM	0x048

#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM	0x048

#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM	0x026

#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM	0x00



#define APPLIED_RESERVED_QUEUE_IN_FW		0x80000000

#define RSVD_FW_QUEUE_PAGE_BK_SHIFT		0x00

#define RSVD_FW_QUEUE_PAGE_BE_SHIFT		0x08
@@ -197,23 +168,6 @@ struct tx_fwinfo_8190pci { 


};





#define TX_DESC_SIZE			32



#define TX_DESC_CMD_SIZE	32





#define TX_STATUS_DESC_SIZE	32



#define TX_FWINFO_SIZE	8





#define RX_DESC_SIZE	16



#define RX_STATUS_DESC_SIZE	16



#define RX_DRIVER_INFO_SIZE	8



struct log_int_8190 {

	u32	nIMR_COMDOK;

	u32	nIMR_MGNTDOK;

drivers/staging/rtl8192e/rtl8192e/r8192E_firmware.h

+0 −2
Original line number Diff line number Diff line
@@ -19,8 +19,6 @@ 
#ifndef __INC_FIRMWARE_H

#define __INC_FIRMWARE_H



#define RTL8190_CPU_START_OFFSET	0x80



#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v)	(4*(v/4) - 8)



#define RTL8192E_BOOT_IMG_FW	"RTL8192E/boot.img"

drivers/staging/rtl8192e/rtl8192e/rtl_dm.c

+0 −3
Original line number Diff line number Diff line
@@ -58,9 +58,6 @@ static u32 edca_setting_UL[HT_IOT_PEER_MAX] = { 
	0x5e4332

};



#define RTK_UL_EDCA 0xa44f

#define RTK_DL_EDCA 0x5e4322



const u32 dm_tx_bb_gain[TxBBGainTableLength] = {

	0x7f8001fe, /* 12 dB */

	0x788001e2, /* 11 dB */

drivers/staging/rtl8192e/rtl8192e/rtl_dm.h

+0 −19
Original line number Diff line number Diff line
@@ -27,26 +27,17 @@ 
#define		DM_DIG_THRESH_HIGH					40

#define		DM_DIG_THRESH_LOW					35



#define		DM_FALSEALARM_THRESH_LOW	40

#define		DM_FALSEALARM_THRESH_HIGH	1000



#define		DM_DIG_HIGH_PWR_THRESH_HIGH		75

#define		DM_DIG_HIGH_PWR_THRESH_LOW		70



#define		BW_AUTO_SWITCH_HIGH_LOW			25

#define		BW_AUTO_SWITCH_LOW_HIGH			30



#define		DM_check_fsync_time_interval				500





#define		DM_DIG_BACKOFF				12

#define		DM_DIG_MAX					0x36

#define		DM_DIG_MIN					0x1c

#define		DM_DIG_MIN_Netcore			0x12



#define		DM_DIG_BACKOFF_MAX			12

#define		DM_DIG_BACKOFF_MIN			-4



#define		RxPathSelection_SS_TH_low		30

#define		RxPathSelection_diff_TH			18
@@ -55,8 +46,6 @@ 
#define		RateAdaptiveTH_Low_40M		10

#define		VeryLowRSSI					15



#define		CTSToSelfTHVal					35



#define		WAIotTHVal						25



#define		E_FOR_TX_POWER_TRACK	       300
@@ -70,14 +59,6 @@ 
#define			Tx_Retry_Count_Reg	 0x1ac

#define		RegC38_TH				 20



#define		TX_POWER_NEAR_FIELD_THRESH_LVL2	74

#define		TX_POWER_NEAR_FIELD_THRESH_LVL1	67



#define		TxHighPwrLevel_Normal		0

#define		TxHighPwrLevel_Level1		1

#define		TxHighPwrLevel_Level2		2



#define		DM_Type_ByFW			0

#define		DM_Type_ByDriver		1



/*--------------------------Define Parameters-------------------------------*/