Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9e6ea59f authored by Bjorn Andersson's avatar Bjorn Andersson Committed by Will Deacon
Browse files

iommu/io-pgtable: Support non-coherent page tables 



Describe the memory related to page table walks as non-cacheable for
iommu instances that are not DMA coherent.

Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
[will: Use cfg->coherent_walk, fix arm-v7s, ensure outer-shareable for NC]
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 4f41845b

drivers/iommu/io-pgtable-arm-v7s.c

+5 −2
Original line number Diff line number Diff line
@@ -789,8 +789,11 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, 
	/* TTBRs */

	cfg->arm_v7s_cfg.ttbr[0] = virt_to_phys(data->pgd) |

				   ARM_V7S_TTBR_S | ARM_V7S_TTBR_NOS |

				   ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |

				   ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA);

				   (cfg->coherent_walk ?

				   (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |

				    ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :

				   (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |

				    ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));

	cfg->arm_v7s_cfg.ttbr[1] = 0;

	return &data->iop;

drivers/iommu/io-pgtable-arm.c

+9 −3
Original line number Diff line number Diff line
@@ -806,9 +806,15 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) 
		return NULL;



	/* TCR */

	if (cfg->coherent_walk) {

		reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |

		      (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |

		      (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);

	} else {

		reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) |

		      (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) |

		      (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_ORGN0_SHIFT);

	}



	switch (ARM_LPAE_GRANULE(data)) {

	case SZ_4K: