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Commit 9e46a48d authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: add support for gen2 pcie link speeds 



Supported on rv6xx/r7xx/evergreen.  Cards come up in gen1 mode.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 3313e3d4

drivers/gpu/drm/radeon/evergreen.c

+53 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 


static void evergreen_gpu_init(struct radeon_device *rdev);

void evergreen_fini(struct radeon_device *rdev);

static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);



void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)

{
@@ -2767,6 +2768,9 @@ static int evergreen_startup(struct radeon_device *rdev) 
{

	int r;



	/* enable pcie gen2 link */

	evergreen_pcie_gen2_enable(rdev);



	if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {

		r = r600_init_microcode(rdev);

		if (r) {
@@ -3049,3 +3053,52 @@ void evergreen_fini(struct radeon_device *rdev) 
	rdev->bios = NULL;

	radeon_dummy_page_fini(rdev);

}



static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)

{

	u32 link_width_cntl, speed_cntl;



	if (rdev->flags & RADEON_IS_IGP)

		return;



	if (!(rdev->flags & RADEON_IS_PCIE))

		return;



	/* x2 cards have a special sequence */

	if (ASIC_IS_X2(rdev))

		return;



	speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);

	if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||

	    (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {



		link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);

		link_width_cntl &= ~LC_UPCONFIGURE_DIS;

		WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);



		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);

		speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;

		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);



		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);

		speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;

		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);



		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);

		speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;

		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);



		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);

		speed_cntl |= LC_GEN2_EN_STRAP;

		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);



	} else {

		link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);

		/* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */

		if (1)

			link_width_cntl |= LC_UPCONFIGURE_DIS;

		else

			link_width_cntl &= ~LC_UPCONFIGURE_DIS;

		WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);

	}

}

drivers/gpu/drm/radeon/evergreend.h

+38 −0
Original line number Diff line number Diff line
@@ -581,6 +581,44 @@ 
#       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)

#       define DC_HPDx_EN                                 (1 << 28)



/* PCIE link stuff */

#define PCIE_LC_TRAINING_CNTL                             0xa1 /* PCIE_P */

#define PCIE_LC_LINK_WIDTH_CNTL                           0xa2 /* PCIE_P */

#       define LC_LINK_WIDTH_SHIFT                        0

#       define LC_LINK_WIDTH_MASK                         0x7

#       define LC_LINK_WIDTH_X0                           0

#       define LC_LINK_WIDTH_X1                           1

#       define LC_LINK_WIDTH_X2                           2

#       define LC_LINK_WIDTH_X4                           3

#       define LC_LINK_WIDTH_X8                           4

#       define LC_LINK_WIDTH_X16                          6

#       define LC_LINK_WIDTH_RD_SHIFT                     4

#       define LC_LINK_WIDTH_RD_MASK                      0x70

#       define LC_RECONFIG_ARC_MISSING_ESCAPE             (1 << 7)

#       define LC_RECONFIG_NOW                            (1 << 8)

#       define LC_RENEGOTIATION_SUPPORT                   (1 << 9)

#       define LC_RENEGOTIATE_EN                          (1 << 10)

#       define LC_SHORT_RECONFIG_EN                       (1 << 11)

#       define LC_UPCONFIGURE_SUPPORT                     (1 << 12)

#       define LC_UPCONFIGURE_DIS                         (1 << 13)

#define PCIE_LC_SPEED_CNTL                                0xa4 /* PCIE_P */

#       define LC_GEN2_EN_STRAP                           (1 << 0)

#       define LC_TARGET_LINK_SPEED_OVERRIDE_EN           (1 << 1)

#       define LC_FORCE_EN_HW_SPEED_CHANGE                (1 << 5)

#       define LC_FORCE_DIS_HW_SPEED_CHANGE               (1 << 6)

#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK      (0x3 << 8)

#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT     3

#       define LC_CURRENT_DATA_RATE                       (1 << 11)

#       define LC_VOLTAGE_TIMER_SEL_MASK                  (0xf << 14)

#       define LC_CLR_FAILED_SPD_CHANGE_CNT               (1 << 21)

#       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 << 23)

#       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 24)

#define MM_CFGREGS_CNTL                                   0x544c

#       define MM_WR_TO_CFG_EN                            (1 << 3)

#define LINK_CNTL2                                        0x88 /* F0 */

#       define TARGET_LINK_SPEED_MASK                     (0xf << 0)

#       define SELECTABLE_DEEMPHASIS                      (1 << 6)



/*

 * PM4

 */

drivers/gpu/drm/radeon/r600.c

+102 −0
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev); 
void r600_gpu_init(struct radeon_device *rdev);

void r600_fini(struct radeon_device *rdev);

void r600_irq_disable(struct radeon_device *rdev);

static void r600_pcie_gen2_enable(struct radeon_device *rdev);



/* get temperature in millidegrees */

u32 rv6xx_get_temp(struct radeon_device *rdev)
@@ -2379,6 +2380,9 @@ int r600_startup(struct radeon_device *rdev) 
{

	int r;



	/* enable pcie gen2 link */

	r600_pcie_gen2_enable(rdev);



	if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {

		r = r600_init_microcode(rdev);

		if (r) {
@@ -3649,3 +3653,101 @@ int r600_get_pcie_lanes(struct radeon_device *rdev) 
	}

}



static void r600_pcie_gen2_enable(struct radeon_device *rdev)

{

	u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;

	u16 link_cntl2;



	if (rdev->flags & RADEON_IS_IGP)

		return;



	if (!(rdev->flags & RADEON_IS_PCIE))

		return;



	/* x2 cards have a special sequence */

	if (ASIC_IS_X2(rdev))

		return;



	/* only RV6xx+ chips are supported */

	if (rdev->family <= CHIP_R600)

		return;



	/* 55 nm r6xx asics */

	if ((rdev->family == CHIP_RV670) ||

	    (rdev->family == CHIP_RV620) ||

	    (rdev->family == CHIP_RV635)) {

		/* advertise upconfig capability */

		link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);

		link_width_cntl &= ~LC_UPCONFIGURE_DIS;

		WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);

		link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);

		if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {

			lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;

			link_width_cntl &= ~(LC_LINK_WIDTH_MASK |

					     LC_RECONFIG_ARC_MISSING_ESCAPE);

			link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;

			WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);

		} else {

			link_width_cntl |= LC_UPCONFIGURE_DIS;

			WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);

		}

	}



	speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);

	if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&

	    (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {



		/* 55 nm r6xx asics */

		if ((rdev->family == CHIP_RV670) ||

		    (rdev->family == CHIP_RV620) ||

		    (rdev->family == CHIP_RV635)) {

			WREG32(MM_CFGREGS_CNTL, 0x8);

			link_cntl2 = RREG32(0x4088);

			WREG32(MM_CFGREGS_CNTL, 0);

			/* not supported yet */

			if (link_cntl2 & SELECTABLE_DEEMPHASIS)

				return;

		}



		speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;

		speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);

		speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;

		speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;

		speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;

		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);



		tmp = RREG32(0x541c);

		WREG32(0x541c, tmp | 0x8);

		WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);

		link_cntl2 = RREG16(0x4088);

		link_cntl2 &= ~TARGET_LINK_SPEED_MASK;

		link_cntl2 |= 0x2;

		WREG16(0x4088, link_cntl2);

		WREG32(MM_CFGREGS_CNTL, 0);



		if ((rdev->family == CHIP_RV670) ||

		    (rdev->family == CHIP_RV620) ||

		    (rdev->family == CHIP_RV635)) {

			training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);

			training_cntl &= ~LC_POINT_7_PLUS_EN;

			WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);

		} else {

			speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);

			speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;

			WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);

		}



		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);

		speed_cntl |= LC_GEN2_EN_STRAP;

		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);



	} else {

		link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);

		/* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */

		if (1)

			link_width_cntl |= LC_UPCONFIGURE_DIS;

		else

			link_width_cntl &= ~LC_UPCONFIGURE_DIS;

		WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);

	}

}

drivers/gpu/drm/radeon/r600d.h

+39 −0
Original line number Diff line number Diff line
@@ -737,6 +737,45 @@ 
#       define DxGRPH_PFLIP_INT_MASK                      (1 << 0)

#       define DxGRPH_PFLIP_INT_TYPE                      (1 << 8)



/* PCIE link stuff */

#define PCIE_LC_TRAINING_CNTL                             0xa1 /* PCIE_P */

#       define LC_POINT_7_PLUS_EN                         (1 << 6)

#define PCIE_LC_LINK_WIDTH_CNTL                           0xa2 /* PCIE_P */

#       define LC_LINK_WIDTH_SHIFT                        0

#       define LC_LINK_WIDTH_MASK                         0x7

#       define LC_LINK_WIDTH_X0                           0

#       define LC_LINK_WIDTH_X1                           1

#       define LC_LINK_WIDTH_X2                           2

#       define LC_LINK_WIDTH_X4                           3

#       define LC_LINK_WIDTH_X8                           4

#       define LC_LINK_WIDTH_X16                          6

#       define LC_LINK_WIDTH_RD_SHIFT                     4

#       define LC_LINK_WIDTH_RD_MASK                      0x70

#       define LC_RECONFIG_ARC_MISSING_ESCAPE             (1 << 7)

#       define LC_RECONFIG_NOW                            (1 << 8)

#       define LC_RENEGOTIATION_SUPPORT                   (1 << 9)

#       define LC_RENEGOTIATE_EN                          (1 << 10)

#       define LC_SHORT_RECONFIG_EN                       (1 << 11)

#       define LC_UPCONFIGURE_SUPPORT                     (1 << 12)

#       define LC_UPCONFIGURE_DIS                         (1 << 13)

#define PCIE_LC_SPEED_CNTL                                0xa4 /* PCIE_P */

#       define LC_GEN2_EN_STRAP                           (1 << 0)

#       define LC_TARGET_LINK_SPEED_OVERRIDE_EN           (1 << 1)

#       define LC_FORCE_EN_HW_SPEED_CHANGE                (1 << 5)

#       define LC_FORCE_DIS_HW_SPEED_CHANGE               (1 << 6)

#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK      (0x3 << 8)

#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT     3

#       define LC_CURRENT_DATA_RATE                       (1 << 11)

#       define LC_VOLTAGE_TIMER_SEL_MASK                  (0xf << 14)

#       define LC_CLR_FAILED_SPD_CHANGE_CNT               (1 << 21)

#       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 << 23)

#       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 24)

#define MM_CFGREGS_CNTL                                   0x544c

#       define MM_WR_TO_CFG_EN                            (1 << 3)

#define LINK_CNTL2                                        0x88 /* F0 */

#       define TARGET_LINK_SPEED_MASK                     (0xf << 0)

#       define SELECTABLE_DEEMPHASIS                      (1 << 6)



/*

 * PM4

 */

drivers/gpu/drm/radeon/radeon.h

+2 −0
Original line number Diff line number Diff line
@@ -1244,6 +1244,8 @@ static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 
 */

#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))

#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))

#define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg))

#define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg))

#define RREG32(reg) r100_mm_rreg(rdev, (reg))

#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))

#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))