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Unverified Commit 9e1975f0 authored by Maxime Ripard's avatar Maxime Ripard
Browse files

ARM: dts: sunxi: Add missing watchdog clocks 



The watchdog has a clock on all our SoCs, but it wasn't always listed.
Add it to the devicetree where it's missing.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent 89d1e514

arch/arm/boot/dts/sun4i-a10.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -816,6 +816,7 @@ 
			compatible = "allwinner,sun4i-a10-wdt";

			reg = <0x01c20c90 0x10>;

			interrupts = <24>;

			clocks = <&osc24M>;

		};



		rtc: rtc@1c20d00 {

arch/arm/boot/dts/sun5i.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -601,6 +601,7 @@ 
			compatible = "allwinner,sun4i-a10-wdt";

			reg = <0x01c20c90 0x10>;

			interrupts = <24>;

			clocks = <&osc24M>;

		};



		ir0: ir@1c21800 {

arch/arm/boot/dts/sun6i-a31.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -745,6 +745,7 @@ 
			compatible = "allwinner,sun6i-a31-wdt";

			reg = <0x01c20ca0 0x20>;

			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&osc24M>;

		};



		spdif: spdif@1c21000 {

arch/arm/boot/dts/sun7i-a20.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -1141,6 +1141,7 @@ 
			compatible = "allwinner,sun4i-a10-wdt";

			reg = <0x01c20c90 0x10>;

			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&osc24M>;

		};



		rtc: rtc@1c20d00 {

arch/arm/boot/dts/sun8i-a23-a33.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -452,6 +452,7 @@ 
			compatible = "allwinner,sun6i-a31-wdt";

			reg = <0x01c20ca0 0x20>;

			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&osc24M>;

		};



		pwm: pwm@1c21400 {