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Commit 9e084bb9 authored by Jiong Wang's avatar Jiong Wang Committed by Daniel Borkmann
Browse files

selftests: bpf: move sub-register zero extension checks into subreg.c 



It is better to centralize all sub-register zero extension checks into an
independent file.

This patch takes the first step to move existing sub-register zero
extension checks into subreg.c.

Acked-by: default avatarJakub Kicinski <jakub.kicinski@netronome.com>
Reviewed-by: default avatarQuentin Monnet <quentin.monnet@netronome.com>
Signed-off-by: default avatarJiong Wang <jiong.wang@netronome.com>
Signed-off-by: default avatarDaniel Borkmann <daniel@iogearbox.net>
parent bd95e678

tools/testing/selftests/bpf/verifier/basic_instr.c

+0 −39
Original line number Diff line number Diff line
@@ -132,42 +132,3 @@ 
	.prog_type = BPF_PROG_TYPE_SCHED_CLS,

	.result = ACCEPT,

},
 
{

	"and32 reg zero extend check",

	.insns = {

	BPF_MOV64_IMM(BPF_REG_0, -1),

	BPF_MOV64_IMM(BPF_REG_2, -2),

	BPF_ALU32_REG(BPF_AND, BPF_REG_0, BPF_REG_2),

	BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),

	BPF_EXIT_INSN(),

	},

	.prog_type = BPF_PROG_TYPE_SCHED_CLS,

	.result = ACCEPT,

	.retval = 0,

},

{

	"or32 reg zero extend check",

	.insns = {

	BPF_MOV64_IMM(BPF_REG_0, -1),

	BPF_MOV64_IMM(BPF_REG_2, -2),

	BPF_ALU32_REG(BPF_OR, BPF_REG_0, BPF_REG_2),

	BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),

	BPF_EXIT_INSN(),

	},

	.prog_type = BPF_PROG_TYPE_SCHED_CLS,

	.result = ACCEPT,

	.retval = 0,

},

{

	"xor32 reg zero extend check",

	.insns = {

	BPF_MOV64_IMM(BPF_REG_0, -1),

	BPF_MOV64_IMM(BPF_REG_2, 0),

	BPF_ALU32_REG(BPF_XOR, BPF_REG_0, BPF_REG_2),

	BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),

	BPF_EXIT_INSN(),

	},

	.prog_type = BPF_PROG_TYPE_SCHED_CLS,

	.result = ACCEPT,

	.retval = 0,

},

tools/testing/selftests/bpf/verifier/subreg.c

0 → 100644
+39 −0
Original line number Diff line number Diff line 
{

	"or32 reg zero extend check",

	.insns = {

	BPF_MOV64_IMM(BPF_REG_0, -1),

	BPF_MOV64_IMM(BPF_REG_2, -2),

	BPF_ALU32_REG(BPF_OR, BPF_REG_0, BPF_REG_2),

	BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),

	BPF_EXIT_INSN(),

	},

	.prog_type = BPF_PROG_TYPE_SCHED_CLS,

	.result = ACCEPT,

	.retval = 0,

},

{

	"and32 reg zero extend check",

	.insns = {

	BPF_MOV64_IMM(BPF_REG_0, -1),

	BPF_MOV64_IMM(BPF_REG_2, -2),

	BPF_ALU32_REG(BPF_AND, BPF_REG_0, BPF_REG_2),

	BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),

	BPF_EXIT_INSN(),

	},

	.prog_type = BPF_PROG_TYPE_SCHED_CLS,

	.result = ACCEPT,

	.retval = 0,

},

{

	"xor32 reg zero extend check",

	.insns = {

	BPF_MOV64_IMM(BPF_REG_0, -1),

	BPF_MOV64_IMM(BPF_REG_2, 0),

	BPF_ALU32_REG(BPF_XOR, BPF_REG_0, BPF_REG_2),

	BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),

	BPF_EXIT_INSN(),

	},

	.prog_type = BPF_PROG_TYPE_SCHED_CLS,

	.result = ACCEPT,

	.retval = 0,

},