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Commit 9d84b51d authored by Jagadeesh Kona's avatar Jagadeesh Kona
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ARM: dts: msm: Mark GCC USB30 secondary clocks as protected on YUPIK 

GCC USB30 secondary clocks are not required on YUPIK, hence mark them
as protected and remove support for USB30 secondary GDSC.

Change-Id: I80abe0f3c10fee6e63a15027f4bd13208e59a795
parent 30e45aae

qcom/yupik.dtsi

+8 −6
Original line number Diff line number Diff line
@@ -942,7 +942,14 @@ 
		<GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>,

		<GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>,

		<GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>,

		<GCC_PCIE_THROTTLE_CORE_CLK>, <GCC_THROTTLE_PCIE_AHB_CLK>;

		<GCC_PCIE_THROTTLE_CORE_CLK>, <GCC_THROTTLE_PCIE_AHB_CLK>,

		<GCC_AGGRE_USB3_SEC_AXI_CLK>, <GCC_CFG_NOC_USB3_SEC_AXI_CLK>,

		<GCC_USB30_SEC_MASTER_CLK>, <GCC_USB30_SEC_MASTER_CLK_SRC>,

		<GCC_USB30_SEC_MOCK_UTMI_CLK>, <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>,

		<GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>,

		<GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>,

		<GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>,

		<GCC_USB3_SEC_PHY_PIPE_CLK_SRC>;



		#clock-cells = <1>;

		#reset-cells = <1>;
@@ -3739,11 +3746,6 @@ 
	status = "ok";

};



&gcc_usb30_sec_gdsc {

	qcom,support-hw-trigger;

	status = "ok";

};



&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {

	status = "ok";

};