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Commit 9d50a8c2 authored by Veera Vegivada's avatar Veera Vegivada
Browse files

ARM: dts: msm: Add qcom,no-accumulative-counter property for cpufreq 

Accumulative cycle counters are not supported, cycle counter needs
to be read from the core-0 of the frequency domain.
Add property to indicate the same.

Change-Id: I503c4470824d29ee95a3c39a172ec716be77c61b
parent eedf5958

qcom/sdmshrike.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -1331,6 +1331,7 @@ 
		reg-names = "freq-domain0", "freq-domain1";

		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

		clock-names = "xo", "alternate";

		qcom,no-accumulative-counter;

		#freq-domain-cells = <2>;

	};

qcom/sm6150.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -1360,6 +1360,7 @@ 
		reg-names = "freq-domain0", "freq-domain1";

		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

		clock-names = "xo", "alternate";

		qcom,no-accumulative-counter;

		#freq-domain-cells = <2>;

	};

qcom/sm8150.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -1068,7 +1068,7 @@ 


		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

		clock-names = "xo", "alternate";



		qcom,no-accumulative-counter;



		#freq-domain-cells = <2>;

	};