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Commit 9d35dc30 authored by Guo Ren's avatar Guo Ren
Browse files

csky: Revert mmu ASID mechanism 



Current C-SKY ASID mechanism is from mips and it doesn't work well
with multi-cores. ASID per core mechanism is not suitable for C-SKY
SMP tlb maintain operations, eg: tlbi.vas need share the same asid
in all processors and it'll invalid the tlb entry in all cores with
the same asid.

This patch is prepare for new ASID mechanism.

Signed-off-by: default avatarGuo Ren <ren_guo@c-sky.com>
Cc: Arnd Bergmann <arnd@arndb.de>
parent 4d581034

arch/csky/include/asm/mmu.h

+0 −1
Original line number Diff line number Diff line
@@ -5,7 +5,6 @@ 
#define __ASM_CSKY_MMU_H



typedef struct {

	unsigned long asid[NR_CPUS];

	void *vdso;

} mm_context_t;

arch/csky/include/asm/mmu_context.h

+7 −105
Original line number Diff line number Diff line
@@ -16,122 +16,24 @@ 


#define TLBMISS_HANDLER_SETUP_PGD(pgd) \

	setup_pgd(__pa(pgd), false)



#define TLBMISS_HANDLER_SETUP_PGD_KERNEL(pgd) \

	setup_pgd(__pa(pgd), true)



#define cpu_context(cpu, mm)	((mm)->context.asid[cpu])

#define cpu_asid(cpu, mm)	(cpu_context((cpu), (mm)) & ASID_MASK)

#define asid_cache(cpu)		(cpu_data[cpu].asid_cache)



#define ASID_FIRST_VERSION	(1 << CONFIG_CPU_ASID_BITS)

#define ASID_INC		0x1

#define ASID_MASK		(ASID_FIRST_VERSION - 1)

#define ASID_VERSION_MASK	~ASID_MASK

#define init_new_context(tsk,mm)	0

#define activate_mm(prev,next)		switch_mm(prev, next, current)



#define destroy_context(mm)		do {} while (0)

#define enter_lazy_tlb(mm, tsk)		do {} while (0)

#define deactivate_mm(tsk, mm)		do {} while (0)



/*

 *  All unused by hardware upper bits will be considered

 *  as a software asid extension.

 */

static inline void

get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)

{

	unsigned long asid = asid_cache(cpu);



	asid += ASID_INC;

	if (!(asid & ASID_MASK)) {

		flush_tlb_all();	/* start new asid cycle */

		if (!asid)		/* fix version if needed */

			asid = ASID_FIRST_VERSION;

	}

	cpu_context(cpu, mm) = asid_cache(cpu) = asid;

}



/*

 * Initialize the context related info for a new mm_struct

 * instance.

 */

static inline int

init_new_context(struct task_struct *tsk, struct mm_struct *mm)

{

	int i;



	for_each_online_cpu(i)

		cpu_context(i, mm) = 0;

	return 0;

}



static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,

switch_mm(struct mm_struct *prev, struct mm_struct *next,

	  struct task_struct *tsk)

{

	unsigned int cpu = smp_processor_id();

	unsigned long flags;



	local_irq_save(flags);

	/* Check if our ASID is of an older version and thus invalid */

	if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)

		get_new_mmu_context(next, cpu);

	write_mmu_entryhi(cpu_asid(cpu, next));

	TLBMISS_HANDLER_SETUP_PGD(next->pgd);



	/*

	 * Mark current->active_mm as not "active" anymore.

	 * We don't want to mislead possible IPI tlb flush routines.

	 */

	cpumask_clear_cpu(cpu, mm_cpumask(prev));

	cpumask_set_cpu(cpu, mm_cpumask(next));



	local_irq_restore(flags);

}



/*

 * After we have set current->mm to a new value, this activates

 * the context for the new mm so we see the new mappings.

 */

static inline void

activate_mm(struct mm_struct *prev, struct mm_struct *next)

{

	unsigned long flags;

	int cpu = smp_processor_id();



	local_irq_save(flags);

	if (prev != next)

		tlb_invalid_all();



	/* Unconditionally get a new ASID.  */

	get_new_mmu_context(next, cpu);



	write_mmu_entryhi(cpu_asid(cpu, next));

	TLBMISS_HANDLER_SETUP_PGD(next->pgd);



	/* mark mmu ownership change */

	cpumask_clear_cpu(cpu, mm_cpumask(prev));

	cpumask_set_cpu(cpu, mm_cpumask(next));



	local_irq_restore(flags);

}



/*

 * If mm is currently active_mm, we can't really drop it. Instead,

 * we will get a new one for it.

 */

static inline void

drop_mmu_context(struct mm_struct *mm, unsigned int cpu)

{

	unsigned long flags;



	local_irq_save(flags);



	if (cpumask_test_cpu(cpu, mm_cpumask(mm)))  {

		get_new_mmu_context(mm, cpu);

		write_mmu_entryhi(cpu_asid(cpu, mm));

	} else {

		/* will get a new context next time */

		cpu_context(cpu, mm) = 0;

	}



	local_irq_restore(flags);

}



#endif /* __ASM_CSKY_MMU_CONTEXT_H */

arch/csky/include/asm/pgtable.h

+0 −2
Original line number Diff line number Diff line
@@ -290,8 +290,6 @@ static inline pte_t *pte_offset(pmd_t *dir, unsigned long address) 
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];

extern void paging_init(void);



extern void show_jtlb_table(void);



void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,

		      pte_t *pte);

arch/csky/kernel/smp.c

+0 −2
Original line number Diff line number Diff line
@@ -212,8 +212,6 @@ void csky_start_secondary(void) 
	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir);

	TLBMISS_HANDLER_SETUP_PGD_KERNEL(swapper_pg_dir);



	asid_cache(smp_processor_id()) = ASID_FIRST_VERSION;



#ifdef CONFIG_CPU_HAS_FPU

	init_fpu();

#endif

arch/csky/mm/init.c

+0 −2
Original line number Diff line number Diff line
@@ -114,8 +114,6 @@ void __init pre_mmu_init(void) 
	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir);

	TLBMISS_HANDLER_SETUP_PGD_KERNEL(swapper_pg_dir);



	asid_cache(smp_processor_id()) = ASID_FIRST_VERSION;



	/* Setup page mask to 4k */

	write_mmu_pagemask(0);

}