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Unverified Commit 9d0fdd48 authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Maxime Ripard
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dt-bindings: display: sunxi: add DT binding for Allwinner H6 DW HDMI 



The Allwinner H6 SoC uses a v2.12a DesignWare HDMI controller, with
dedicated CEC and HDCP clocks added; the PHY connected is a standard
DesignWare HDMI PHY.

Add binding for it.

Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
[added HDCP clock and reset]
Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181104182705.18047-19-jernej.skrabec@siol.net
parent 76ce87ca

Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt

+9 −2
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ Required properties: 
  - compatible: value must be one of:

    * "allwinner,sun8i-a83t-dw-hdmi"

    * "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"

    * "allwinner,sun50i-h6-dw-hdmi"

  - reg: base address and size of memory-mapped region

  - reg-io-width: See dw_hdmi.txt. Shall be 1.

  - interrupts: HDMI interrupt number
@@ -86,9 +87,14 @@ Required properties: 
    * iahb: the HDMI bus clock

    * isfr: the HDMI register clock

    * tmds: TMDS clock

    * cec: HDMI CEC clock (H6 only)

    * hdcp: HDCP clock (H6 only)

    * hdcp-bus: HDCP bus clock (H6 only)

  - clock-names: the clock names mentioned above

  - resets: phandle to the reset controller

  - reset-names: must be "ctrl"

  - resets:

    * ctrl: HDMI controller reset

    * hdcp: HDCP reset (H6 only)

  - reset-names: reset names mentioned above

  - phys: phandle to the DWC HDMI PHY

  - phy-names: must be "phy"
@@ -109,6 +115,7 @@ Required properties: 
    * allwinner,sun8i-h3-hdmi-phy

    * allwinner,sun8i-r40-hdmi-phy

    * allwinner,sun50i-a64-hdmi-phy

    * allwinner,sun50i-h6-hdmi-phy

  - reg: base address and size of memory-mapped region

  - clocks: phandles to the clocks feeding the HDMI PHY

    * bus: the HDMI PHY interface clock