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Commit 9cc2a0c9 authored by Padmavathi Venna's avatar Padmavathi Venna Committed by Sylwester Nawrocki
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clk: samsung: exynos7: add gate clock for DMA block 



Add support for PDMA0 and PDMA1 gate clks.

Signed-off-by: default avatarPadmavathi Venna <padma.v@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent 83f191a7

drivers/clk/samsung/clk-exynos7.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -722,6 +722,10 @@ static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { 
	GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",

	GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",

		"mout_aclk_fsys0_200_user",

		"mout_aclk_fsys0_200_user",

		ENABLE_ACLK_FSYS00, 19, 0, 0),

		ENABLE_ACLK_FSYS00, 19, 0, 0),

	GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",

			ENABLE_ACLK_FSYS00, 3, 0, 0),

	GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",

			ENABLE_ACLK_FSYS00, 4, 0, 0),





	GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",

	GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",

		ENABLE_ACLK_FSYS01, 29, 0, 0),

		ENABLE_ACLK_FSYS01, 29, 0, 0),

include/dt-bindings/clock/exynos7-clk.h

+3 −1
Original line number Original line Diff line number Diff line
@@ -91,7 +91,9 @@ 
#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER		6

#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER		6

#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER		7

#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER		7

#define OSCCLK_PHY_CLKOUT_USB30_PHY		8

#define OSCCLK_PHY_CLKOUT_USB30_PHY		8

#define FSYS0_NR_CLK			9

#define ACLK_PDMA0			9

#define ACLK_PDMA1			10

#define FSYS0_NR_CLK			11





/* FSYS1 */

/* FSYS1 */

#define ACLK_MMC1			1

#define ACLK_MMC1			1