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Commit 9caec662 authored by Jon Hunter's avatar Jon Hunter Committed by Stephen Boyd
Browse files

clk: tegra210: Fix default rates for HDA clocks 



Currently the default clock rates for the HDA and HDA2CODEC_2X clocks
are both 19.2MHz. However, the default rates for these clocks should
actually be 51MHz and 48MHz, respectively. The current clock settings
results in a distorted output during audio playback. Correct the default
clock rates for these clocks by specifying them in the clock init table
for Tegra210.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent f18d4304

drivers/clk/tegra/clk-tegra210.c

+2 −0
Original line number Diff line number Diff line
@@ -3377,6 +3377,8 @@ static struct tegra_clk_init_table init_table[] __initdata = { 
	{ TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },

	{ TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },

	{ TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },

	{ TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },

	{ TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },

	/* This MUST be the last entry. */

	{ TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },

};