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Commit 9c8c6bad authored by Cyrill Gorcunov's avatar Cyrill Gorcunov Committed by Ingo Molnar
Browse files

x86, perf: Fix few cosmetic dabs for P4 pmu (comments and constantify) 



- A few ESCR have escaped fixing at previous attempt.
- p4_escr_map is read only, make it const.

Nothing serious.

Signed-off-by: default avatarCyrill Gorcunov <gorcunov@openvz.org>
Cc: Lin Ming <ming.m.lin@intel.com>
LKML-Reference: <20100318211256.GH5062@lenovo>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 4b24a88b

arch/x86/include/asm/perf_event_p4.h

+2 −2
Original line number Diff line number Diff line
@@ -401,13 +401,13 @@ static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr) 
#define P4_RETIRED_MISPRED_BRANCH_TYPE	P4_EVENT_PACK(0x05, 0x02)

	/*

	 * MSR_P4_TBPU_ESCR0:	4, 5

	 * MSR_P4_TBPU_ESCR0:	6, 7

	 * MSR_P4_TBPU_ESCR1:	6, 7

	 */



#define P4_RETIRED_BRANCH_TYPE		P4_EVENT_PACK(0x04, 0x02)

	/*

	 * MSR_P4_TBPU_ESCR0:	4, 5

	 * MSR_P4_TBPU_ESCR0:	6, 7

	 * MSR_P4_TBPU_ESCR1:	6, 7

	 */



#define P4_RESOURCE_STALL		P4_EVENT_PACK(0x01, 0x01)

arch/x86/kernel/cpu/perf_event_p4.c

+1 −1
Original line number Diff line number Diff line
@@ -545,7 +545,7 @@ static void p4_pmu_swap_config_ts(struct hw_perf_event *hwc, int cpu) 
}



/* ESCRs are not sequential in memory so we need a map */

static unsigned int p4_escr_map[ARCH_P4_TOTAL_ESCR] = {

static const unsigned int p4_escr_map[ARCH_P4_TOTAL_ESCR] = {

	MSR_P4_ALF_ESCR0,	/*  0 */

	MSR_P4_ALF_ESCR1,	/*  1 */

	MSR_P4_BPU_ESCR0,	/*  2 */