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Commit 9c3250a1 authored by Daniel Klamt's avatar Daniel Klamt Committed by Michael Ellerman
Browse files

powerpc/xive: Replace msleep(x) with msleep(OPAL_BUSY_DELAY_MS) 



Replace msleep(x) with with msleep(OPAL_BUSY_DELAY_MS) to document
these sleeps are to wait for opal (firmware).

Signed-off-by: default avatarDaniel Klamt <eleon@ele0n.de>
Signed-off-by: default avatarBjoern Noetel <bjoern@br3ak3r.de>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 54dbcfc2

arch/powerpc/sysdev/xive/native.c

+12 −12
Original line number Diff line number Diff line
@@ -109,7 +109,7 @@ int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) 
		rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq);

		if (rc != OPAL_BUSY)

			break;

		msleep(1);

		msleep(OPAL_BUSY_DELAY_MS);

	}

	return rc == 0 ? 0 : -ENXIO;

}
@@ -163,7 +163,7 @@ int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, 
		rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags);

		if (rc != OPAL_BUSY)

			break;

		msleep(1);

		msleep(OPAL_BUSY_DELAY_MS);

	}

	if (rc) {

		pr_err("Error %lld setting queue for prio %d\n", rc, prio);
@@ -190,7 +190,7 @@ static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) 
		rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0);

		if (rc != OPAL_BUSY)

			break;

		msleep(1);

		msleep(OPAL_BUSY_DELAY_MS);

	}

	if (rc)

		pr_err("Error %lld disabling queue for prio %d\n", rc, prio);
@@ -253,7 +253,7 @@ static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc) 
	for (;;) {

		irq = opal_xive_allocate_irq(chip_id);

		if (irq == OPAL_BUSY) {

			msleep(1);

			msleep(OPAL_BUSY_DELAY_MS);

			continue;

		}

		if (irq < 0) {
@@ -275,7 +275,7 @@ u32 xive_native_alloc_irq(void) 
		rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP);

		if (rc != OPAL_BUSY)

			break;

		msleep(1);

		msleep(OPAL_BUSY_DELAY_MS);

	}

	if (rc < 0)

		return 0;
@@ -289,7 +289,7 @@ void xive_native_free_irq(u32 irq) 
		s64 rc = opal_xive_free_irq(irq);

		if (rc != OPAL_BUSY)

			break;

		msleep(1);

		msleep(OPAL_BUSY_DELAY_MS);

	}

}

EXPORT_SYMBOL_GPL(xive_native_free_irq);
@@ -305,7 +305,7 @@ static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc) 
	for (;;) {

		rc = opal_xive_free_irq(xc->hw_ipi);

		if (rc == OPAL_BUSY) {

			msleep(1);

			msleep(OPAL_BUSY_DELAY_MS);

			continue;

		}

		xc->hw_ipi = 0;
@@ -400,7 +400,7 @@ static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc) 
		rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0);

		if (rc != OPAL_BUSY)

			break;

		msleep(1);

		msleep(OPAL_BUSY_DELAY_MS);

	}

	if (rc) {

		pr_err("Failed to enable pool VP on CPU %d\n", cpu);
@@ -444,7 +444,7 @@ static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) 
		rc = opal_xive_set_vp_info(vp, 0, 0);

		if (rc != OPAL_BUSY)

			break;

		msleep(1);

		msleep(OPAL_BUSY_DELAY_MS);

	}

}
@@ -645,7 +645,7 @@ u32 xive_native_alloc_vp_block(u32 max_vcpus) 
		rc = opal_xive_alloc_vp_block(order);

		switch (rc) {

		case OPAL_BUSY:

			msleep(1);

			msleep(OPAL_BUSY_DELAY_MS);

			break;

		case OPAL_XIVE_PROVISIONING:

			if (!xive_native_provision_pages())
@@ -687,7 +687,7 @@ int xive_native_enable_vp(u32 vp_id, bool single_escalation) 
		rc = opal_xive_set_vp_info(vp_id, flags, 0);

		if (rc != OPAL_BUSY)

			break;

		msleep(1);

		msleep(OPAL_BUSY_DELAY_MS);

	}

	return rc ? -EIO : 0;

}
@@ -701,7 +701,7 @@ int xive_native_disable_vp(u32 vp_id) 
		rc = opal_xive_set_vp_info(vp_id, 0, 0);

		if (rc != OPAL_BUSY)

			break;

		msleep(1);

		msleep(OPAL_BUSY_DELAY_MS);

	}

	return rc ? -EIO : 0;

}