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Commit 9c2cbd47 authored by Antoine Tenart's avatar Antoine Tenart Committed by David S. Miller
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Documentation/bindings: phy: document the Marvell comphy driver 



The Marvell Armada 7K/8K SoCs contains an hardware block called COMPHY
that provides a number of shared PHYs used by various interfaces in the
SoC: network, SATA, PCIe, etc. This Device Tree binding allows to
describe this COMPHY hardware block.

Signed-off-by: default avatarAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d0438bd6

Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt

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mvebu comphy driver

-------------------



A comphy controller can be found on Marvell Armada 7k/8k on the CP110. It

provides a number of shared PHYs used by various interfaces (network, sata,

usb, PCIe...).



Required properties:



- compatible: should be "marvell,comphy-cp110"

- reg: should contain the comphy register location and length.

- marvell,system-controller: should contain a phandle to the

                             system controller node.

- #address-cells: should be 1.

- #size-cells: should be 0.



A sub-node is required for each comphy lane provided by the comphy.



Required properties (child nodes):



- reg: comphy lane number.

- #phy-cells : from the generic phy bindings, must be 1. Defines the

               input port to use for a given comphy lane.



Example:



	cpm_comphy: phy@120000 {

		compatible = "marvell,comphy-cp110";

		reg = <0x120000 0x6000>;

		marvell,system-controller = <&cpm_syscon0>;

		#address-cells = <1>;

		#size-cells = <0>;



		cpm_comphy0: phy@0 {

			reg = <0>;

			#phy-cells = <1>;

		};



		cpm_comphy1: phy@1 {

			reg = <1>;

			#phy-cells = <1>;

		};

	};