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Commit 9c0e5c70 authored by Jeevan Shriram's avatar Jeevan Shriram Committed by Elliot Berman
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drivers: pinctrl: Add support for read/write of QUP registers 



Add support to read and write QUP mode registers in TLMM block.

Change-Id: I9878af50f6920c577fa74047e01e9b37c0542dd1
Signed-off-by: default avatarRishabh Bhatnagar <rishabhb@codeaurora.org>
Signed-off-by: default avatarJeevan Shriram <jshriram@codeaurora.org>
[eberman@codeaurora.org: reintroduce msm_pinctrl_data]
Signed-off-by: default avatarElliot Berman <eberman@codeaurora.org>
parent c4787643

drivers/pinctrl/qcom/pinctrl-msm.c

+42 −1
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#include <linux/reboot.h>

#include <linux/pm.h>

#include <linux/log2.h>

#include <linux/bitmap.h>



#include "../core.h"

#include "../pinconf.h"
@@ -31,6 +32,7 @@ 
#define MAX_NR_GPIO 300

#define MAX_NR_TILES 4

#define PS_HOLD_OFFSET 0x820

#define QUP_MASK       GENMASK(5, 0)



/**

 * struct msm_pinctrl - state for a pinctrl-msm device
@@ -66,6 +68,8 @@ struct msm_pinctrl { 
	void __iomem *regs[MAX_NR_TILES];

};



static struct msm_pinctrl *msm_pinctrl_data;



#define MSM_ACCESSOR(name) \

static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \

			    const struct msm_pingroup *g) \
@@ -1128,6 +1132,42 @@ SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend, 


EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);



int msm_qup_write(u32 mode, u32 val)

{

	int i;

	struct pinctrl_qup *regs = msm_pinctrl_data->soc->qup_regs;

	int num_regs =  msm_pinctrl_data->soc->nqup_regs;



	/*Iterate over modes*/

	for (i = 0; i < num_regs; i++) {

		if (regs[i].mode == mode) {

			writel_relaxed(val & QUP_MASK,

				 msm_pinctrl_data->regs[0] + regs[i].offset);

			return 0;

		}

	}



	return -ENOENT;

}



int msm_qup_read(unsigned int mode)

{

	int i, val;

	struct pinctrl_qup *regs = msm_pinctrl_data->soc->qup_regs;

	int num_regs =  msm_pinctrl_data->soc->nqup_regs;



	/*Iterate over modes*/

	for (i = 0; i < num_regs; i++) {

		if (regs[i].mode == mode) {

			val = readl_relaxed(msm_pinctrl_data->regs[0] +

								regs[i].offset);

			return val & QUP_MASK;

		}

	}



	return -ENOENT;

}



int msm_pinctrl_probe(struct platform_device *pdev,

		      const struct msm_pinctrl_soc_data *soc_data)

{
@@ -1136,7 +1176,8 @@ int msm_pinctrl_probe(struct platform_device *pdev, 
	int ret;

	int i;



	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);

	msm_pinctrl_data = pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl),

						GFP_KERNEL);

	if (!pctrl)

		return -ENOMEM;

drivers/pinctrl/qcom/pinctrl-msm.h

+14 −0
Original line number Diff line number Diff line
@@ -5,6 +5,8 @@ 
#ifndef __PINCTRL_MSM_H__

#define __PINCTRL_MSM_H__



#include <linux/pinctrl/qcom-pinctrl.h>



struct pinctrl_pin_desc;



/**
@@ -93,6 +95,16 @@ struct msm_pingroup { 
	unsigned intr_detection_width:5;

};



/*

 * struct pinctrl_qup - Qup mode configuration

 * @mode:	Qup i3c mode

 * @offset:	Offset of the register

 */

struct pinctrl_qup {

	u32 mode;

	u32 offset;

};



/**

 * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration

 * @pins:	    An array describing all pins the pin controller affects.
@@ -116,6 +128,8 @@ struct msm_pinctrl_soc_data { 
	const char *const *tiles;

	unsigned int ntiles;

	const int *reserved_gpios;

	struct pinctrl_qup *qup_regs;

	unsigned int nqup_regs;

};



extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;

include/linux/pinctrl/qcom-pinctrl.h

0 → 100644
+14 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#ifndef __LINUX_PINCTRL_MSM_H__

#define __LINUX_PINCTRL_MSM_H__



/* APIS to access qup_i3c registers */

int msm_qup_write(u32 mode, u32 val);

int msm_qup_read(u32 mode);





#endif /* __LINUX_PINCTRL_MSM_H__ */