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Commit 9bb03d26 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx-dt-clkdep-5.3' of... 

Merge tag 'imx-dt-clkdep-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX DT changes with new clock for 5.3:
 - This is a set of device tree changes with new clocks - adding
   clock info for i.MX8 GPIO and SNVS RTC device.

* tag 'imx-dt-clkdep-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux

:
  arm64: dts: imx8mq: add clock for SNVS RTC node
  arm64: dts: imx8mm: add clock for SNVS RTC node
  arm64: dts: imx8mm: add clock for GPIO node
  clk: imx8m: Add GIC clock
  dt-bindings: clock: imx8m: Add GIC clock
  clk: imx8mm: add SNVS clock to clock tree
  dt-bindings: clock: imx8mm: Add SNVS clock
  clk: imx8mq: add SNVS clock to clock tree
  dt-bindings: clock: imx8mq: Add SNVS clock
  clk: imx8mm: add GPIO clocks to clock tree
  dt-bindings: clock: imx8mm: Add GPIO clocks

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents c529cbb5 881b54c7

arch/arm64/boot/dts/freescale/imx8mm.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -206,6 +206,7 @@ 
				reg = <0x30200000 0x10000>;

				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;
@@ -217,6 +218,7 @@ 
				reg = <0x30210000 0x10000>;

				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;
@@ -228,6 +230,7 @@ 
				reg = <0x30220000 0x10000>;

				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;
@@ -239,6 +242,7 @@ 
				reg = <0x30230000 0x10000>;

				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;
@@ -250,6 +254,7 @@ 
				reg = <0x30240000 0x10000>;

				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;
@@ -336,6 +341,8 @@ 
					offset = <0x34>;

					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,

						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

					clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;

					clock-names = "snvs-rtc";

				};



				snvs_pwrkey: snvs-powerkey {

arch/arm64/boot/dts/freescale/imx8mq.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -433,6 +433,8 @@ 
					offset = <0x34>;

					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,

						<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

					clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;

					clock-names = "snvs-rtc";

				};



			};

drivers/clk/imx/clk-imx8mm.c

+10 −0
Original line number Diff line number Diff line
@@ -288,6 +288,9 @@ static const char *imx8mm_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pl 
static const char *imx8mm_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",

					     "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };



static const char *imx8mm_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll2_100m",

					"sys_pll1_800m", "clk_ext2", "clk_ext4", "audio_pll2_out" };



static const char *imx8mm_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",

					   "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
@@ -558,6 +561,7 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node) 
	clks[IMX8MM_CLK_UART4] = imx8m_clk_composite("uart4", imx8mm_uart4_sels, base + 0xb080);

	clks[IMX8MM_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100);

	clks[IMX8MM_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180);

	clks[IMX8MM_CLK_GIC] = imx8m_clk_composite_critical("gic", imx8mm_gic_sels, base + 0xb200);

	clks[IMX8MM_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280);

	clks[IMX8MM_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300);

	clks[IMX8MM_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380);
@@ -590,6 +594,11 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node) 
	clks[IMX8MM_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);

	clks[IMX8MM_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);

	clks[IMX8MM_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);

	clks[IMX8MM_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0);

	clks[IMX8MM_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0);

	clks[IMX8MM_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);

	clks[IMX8MM_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);

	clks[IMX8MM_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);

	clks[IMX8MM_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0);

	clks[IMX8MM_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);

	clks[IMX8MM_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
@@ -617,6 +626,7 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node) 
	clks[IMX8MM_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);

	clks[IMX8MM_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);

	clks[IMX8MM_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);

	clks[IMX8MM_CLK_SNVS_ROOT] = imx_clk_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);

	clks[IMX8MM_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);

	clks[IMX8MM_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);

	clks[IMX8MM_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);

drivers/clk/imx/clk-imx8mq.c

+5 −0
Original line number Diff line number Diff line
@@ -192,6 +192,9 @@ static const char * const imx8mq_usb_core_sels[] = {"osc_25m", "sys1_pll_100m", 
static const char * const imx8mq_usb_phy_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m",

					     "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };



static const char * const imx8mq_gic_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys2_pll_100m",

					       "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out" };



static const char * const imx8mq_ecspi1_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",

					   "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
@@ -442,6 +445,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) 
	clks[IMX8MQ_CLK_UART4] = imx8m_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb080);

	clks[IMX8MQ_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mq_usb_core_sels, base + 0xb100);

	clks[IMX8MQ_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180);

	clks[IMX8MQ_CLK_GIC] = imx8m_clk_composite_critical("gic", imx8mq_gic_sels, base + 0xb200);

	clks[IMX8MQ_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mq_ecspi1_sels, base + 0xb280);

	clks[IMX8MQ_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mq_ecspi2_sels, base + 0xb300);

	clks[IMX8MQ_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mq_pwm1_sels, base + 0xb380);
@@ -507,6 +511,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) 
	clks[IMX8MQ_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);

	clks[IMX8MQ_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);

	clks[IMX8MQ_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);

	clks[IMX8MQ_CLK_SNVS_ROOT] = imx_clk_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);

	clks[IMX8MQ_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);

	clks[IMX8MQ_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);

	clks[IMX8MQ_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);

include/dt-bindings/clock/imx8mm-clock.h

+10 −1
Original line number Diff line number Diff line
@@ -239,6 +239,15 @@ 


#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK	222



#define IMX8MM_CLK_END				223

#define IMX8MM_CLK_GPIO1_ROOT			223

#define IMX8MM_CLK_GPIO2_ROOT			224

#define IMX8MM_CLK_GPIO3_ROOT			225

#define IMX8MM_CLK_GPIO4_ROOT			226

#define IMX8MM_CLK_GPIO5_ROOT			227



#define IMX8MM_CLK_SNVS_ROOT			228

#define IMX8MM_CLK_GIC				229



#define IMX8MM_CLK_END				230



#endif