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Commit 9baf7d6b authored by Neil Armstrong's avatar Neil Armstrong Committed by Kevin Hilman
Browse files

arm64: dts: meson: g12a: Add G12A USB nodes 



This patch adds the nodes for the USB Complex found in the Amlogic
G12A SoC.

It includes the :
- 2 USB2 PHYs
- 1 USB3 + PCIE Combo PHY
- the USB Glue with it's DWC2 and DWC3 sub-nodes

Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent 820873cf

arch/arm64/boot/dts/amlogic/meson-g12a.dtsi

+75 −0
Original line number Diff line number Diff line
@@ -3,11 +3,13 @@ 
 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.

 */



#include <dt-bindings/phy/phy.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/clock/g12a-clkc.h>

#include <dt-bindings/clock/g12a-aoclkc.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>



/ {

	compatible = "amlogic,g12a";
@@ -183,6 +185,26 @@ 
				};

			};



			usb2_phy0: phy@36000 {

				compatible = "amlogic,g12a-usb2-phy";

				reg = <0x0 0x36000 0x0 0x2000>;

				clocks = <&xtal>;

				clock-names = "xtal";

				resets = <&reset RESET_USB_PHY20>;

				reset-names = "phy";

				#phy-cells = <0>;

			};



			usb2_phy1: phy@3a000 {

				compatible = "amlogic,g12a-usb2-phy";

				reg = <0x0 0x3a000 0x0 0x2000>;

				clocks = <&xtal>;

				clock-names = "xtal";

				resets = <&reset RESET_USB_PHY21>;

				reset-names = "phy";

				#phy-cells = <0>;

			};



			hiu: bus@3c000 {

				compatible = "simple-bus";

				reg = <0x0 0x3c000 0x0 0x1400>;
@@ -203,6 +225,18 @@ 
					};

				};

			};



			usb3_pcie_phy: phy@46000 {

				compatible = "amlogic,g12a-usb3-pcie-phy";

				reg = <0x0 0x46000 0x0 0x2000>;

				clocks = <&clkc CLKID_PCIE_PLL>;

				clock-names = "ref_clk";

				resets = <&reset RESET_PCIE_PHY>;

				reset-names = "phy";

				assigned-clocks = <&clkc CLKID_PCIE_PLL>;

				assigned-clock-rates = <100000000>;

				#phy-cells = <1>;

			};

		};



		aobus: bus@ff800000 {
@@ -366,6 +400,47 @@ 
				status = "disabled";

			};

		};



		usb: usb@ffe09000 {

			status = "disabled";

			compatible = "amlogic,meson-g12a-usb-ctrl";

			reg = <0x0 0xffe09000 0x0 0xa0>;

			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			clocks = <&clkc CLKID_USB>;

			resets = <&reset RESET_USB>;



			dr_mode = "otg";



			phys = <&usb2_phy0>, <&usb2_phy1>,

			       <&usb3_pcie_phy PHY_TYPE_USB3>;

			phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";



			dwc2: usb@ff400000 {

				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";

				reg = <0x0 0xff400000 0x0 0x40000>;

				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;

				clock-names = "ddr";

				phys = <&usb2_phy1>;

				dr_mode = "peripheral";

				g-rx-fifo-size = <192>;

				g-np-tx-fifo-size = <128>;

				g-tx-fifo-size = <128 128 16 16 16>;

			};



			dwc3: usb@ff500000 {

				compatible = "snps,dwc3";

				reg = <0x0 0xff500000 0x0 0x100000>;

				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;

				dr_mode = "host";

				snps,dis_u2_susphy_quirk;

				snps,quirk-frame-length-adjustment;

			};

		};

	};



	timer {