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Commit 9b6de0a1 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Only wait for required lanes in vlv_wait_port_ready() 



Currently vlv_wait_port_ready() waits for all four lanes on the
appropriate channel. This no longer works on CHV when the unused
lanes may be power gated. So pass in a mask of lanes that the
caller is expecting to be ready.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDeepak <S&lt;deepak.s@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent c7c7372e

drivers/gpu/drm/i915/intel_display.c

+6 −4
Original line number Diff line number Diff line
@@ -1844,7 +1844,8 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 
}



void vlv_wait_port_ready(struct drm_i915_private *dev_priv,

		struct intel_digital_port *dport)

			 struct intel_digital_port *dport,

			 unsigned int expected_mask)

{

	u32 port_mask;

	int dpll_reg;
@@ -1857,6 +1858,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 
	case PORT_C:

		port_mask = DPLL_PORTC_READY_MASK;

		dpll_reg = DPLL(0);

		expected_mask <<= 4;

		break;

	case PORT_D:

		port_mask = DPLL_PORTD_READY_MASK;
@@ -1866,9 +1868,9 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 
		BUG();

	}



	if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))

		WARN(1, "timed out waiting for port %c ready: 0x%08x\n",

		     port_name(dport->port), I915_READ(dpll_reg));

	if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))

		WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",

		     port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);

}



static void intel_prepare_shared_dpll(struct intel_crtc *crtc)

drivers/gpu/drm/i915/intel_dp.c

+3 −1
Original line number Diff line number Diff line
@@ -2497,6 +2497,7 @@ static void intel_enable_dp(struct intel_encoder *encoder) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

	uint32_t dp_reg = I915_READ(intel_dp->output_reg);

	unsigned int lane_mask = 0x0;



	if (WARN_ON(dp_reg & DP_PORT_EN))

		return;
@@ -2515,7 +2516,8 @@ static void intel_enable_dp(struct intel_encoder *encoder) 
	pps_unlock(intel_dp);



	if (IS_VALLEYVIEW(dev))

		vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));

		vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),

				    lane_mask);



	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);

	intel_dp_start_link_train(intel_dp);

drivers/gpu/drm/i915/intel_drv.h

+2 −1
Original line number Diff line number Diff line
@@ -1013,7 +1013,8 @@ intel_wait_for_vblank(struct drm_device *dev, int pipe) 
}

int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);

void vlv_wait_port_ready(struct drm_i915_private *dev_priv,

			 struct intel_digital_port *dport);

			 struct intel_digital_port *dport,

			 unsigned int expected_mask);

bool intel_get_load_detect_pipe(struct drm_connector *connector,

				struct drm_display_mode *mode,

				struct intel_load_detect_pipe *old,

drivers/gpu/drm/i915/intel_hdmi.c

+2 −2
Original line number Diff line number Diff line
@@ -1324,7 +1324,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) 


	intel_enable_hdmi(encoder);



	vlv_wait_port_ready(dev_priv, dport);

	vlv_wait_port_ready(dev_priv, dport, 0x0);

}



static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
@@ -1641,7 +1641,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) 


	intel_enable_hdmi(encoder);



	vlv_wait_port_ready(dev_priv, dport);

	vlv_wait_port_ready(dev_priv, dport, 0x0);

}



static void intel_hdmi_destroy(struct drm_connector *connector)