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Commit 9b11215e authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Flatten and rename haswell_set_pipemisc() 



Move the platform checks out from haswell_set_pipemisc() and
rename it to bdw_set_pipemisc() to make it clear when to call it.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190412183009.8237-1-ville.syrjala@linux.intel.com


Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 8a9b36e2

drivers/gpu/drm/i915/intel_display.c

+33 −35
Original line number Diff line number Diff line
@@ -126,7 +126,7 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta 
static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);

static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);

static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);

static void haswell_set_pipemisc(const struct intel_crtc_state *crtc_state);

static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);

static void vlv_prepare_pll(struct intel_crtc *crtc,

			    const struct intel_crtc_state *pipe_config);

static void chv_prepare_pll(struct intel_crtc *crtc,
@@ -6043,7 +6043,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, 
	if (!transcoder_is_dsi(cpu_transcoder))

		haswell_set_pipeconf(pipe_config);



	haswell_set_pipemisc(pipe_config);

	if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))

		bdw_set_pipemisc(pipe_config);



	intel_crtc->active = true;
@@ -8890,12 +8891,10 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state) 
	POSTING_READ(PIPECONF(cpu_transcoder));

}



static void haswell_set_pipemisc(const struct intel_crtc_state *crtc_state)

static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);

	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);



	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	u32 val = 0;



	switch (crtc_state->pipe_bpp) {
@@ -8912,8 +8911,8 @@ static void haswell_set_pipemisc(const struct intel_crtc_state *crtc_state) 
		val |= PIPEMISC_DITHER_12_BPC;

		break;

	default:

			/* Case prevented by pipe_config_set_bpp. */

			BUG();

		MISSING_CASE(crtc_state->pipe_bpp);

		break;

	}



	if (crtc_state->dither)
@@ -8927,8 +8926,7 @@ static void haswell_set_pipemisc(const struct intel_crtc_state *crtc_state) 
		val |= PIPEMISC_YUV420_ENABLE |

			PIPEMISC_YUV420_MODE_FULL_BLEND;



		I915_WRITE(PIPEMISC(intel_crtc->pipe), val);

	}

	I915_WRITE(PIPEMISC(crtc->pipe), val);

}



int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)