Loading bindings/pinctrl/qcom,slpi-pinctrl.txt 0 → 100644 +123 −0 Original line number Diff line number Diff line Qualcomm Technologies, Inc. SLPI Pin controller driver This DT bindings describes the Pin controller driver being added for supporting SLPI (Sensor Low Power Island) TLMM from QTI chipsets. Following properties are for SLPI Pin controller device main node. - compatible: Usage: required Value type: <string> Definition: must be "qcom,slpi-pinctrl" - reg: Usage: required Value type: <prop-encoded-array> Definition: Base address and size of the SLPI TLMM register space. - qcom,num-pins: Usage: required Value type: <u32> Definition: Number of PINs supported by the SLPI TLMM. Please refer to pinctrl-bindings.txt in this directory for details of the common pinctrl bindings used by client devices, including the meaning of the phrase "pin configuration node". The pin configuration nodes act as a container for an arbitrary number of subnodes. Each of these subnodes represents some desired configuration for a pin or a list of pins. This configuration can include the mux function to select on those pin(s), and various pin configuration parameters, as listed below. SUBNODES: The name of each subnode is not important; all subnodes should be enumerated and processed purely based on their content. Each subnode only affects those parameters that are explicitly listed. In other words, a subnode that lists a mux function but no pin configuration parameters implies no information about any pin configuration parameters. Similarly, a pin subnode that describes a pullup parameter implies no information about e.g. the mux function. The following generic properties as defined in pinctrl-bindings.txt are valid to specify in a pin configuration subnode: - pins: Usage: required Value type: <string-array> Definition: List of gpio pins affected by the properties specified in this subnode. Valid pins are: gpio0-gpio31 for LPI. - function: Usage: required Value type: <string> Definition: Specify the alternative function to be configured for the specified pins. Valid values are: "gpio", "func1", "func2", "func3", "func4", "func5" - bias-disable: Usage: optional Value type: <none> Definition: The specified pins should be configured as no pull. - bias-pull-down: Usage: optional Value type: <none> Definition: The specified pins should be configured as pull down. - bias-bus-hold: Usage: optional Value type: <none> Definition: The specified pins should be configured as bus-keeper mode. - bias-pull-up: Usage: optional Value type: <empty> Definition: The specified pins should be configured as pull up. - qcom,drive-strength: Usage: optional Value type: <u32> Definition: Selects the drive strength for the specified pins. Example: slpi_tlmm: slpi_pinctrl@02b40000 { compatible = "qcom,slpi-pinctrl"; qcom,num-pins = <14>; reg = <0x02b40000 0x20000>; slpi_mclk0_active: slpi_mclk0_active { mux { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "func2"; }; config { pins = "gpio0", "gpio1", "gpio2", "gpio3"; drive-strength = <8>; bias-disable; }; }; slpi_mclk0_sleep: slpi_mclk0_sleep { mux { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "func2"; }; config { pins = "gpio0", "gpio1", "gpio2", "gpio3"; drive-strength = <2>; bias-pull-down; }; }; }; qcom/sa8155.dtsi +4 −0 Original line number Diff line number Diff line Loading @@ -49,5 +49,9 @@ /delete-node/ rpmh-regulator-ldof6; }; &slpi_tlmm { status = "ok"; }; /* Add regulator nodes specific to SA8155 */ #include "sa8155-regulator.dtsi" qcom/sm8150-slpi-pinctrl.dtsi 0 → 100644 +186 −0 Original line number Diff line number Diff line &soc { slpi_tlmm: slpi_pinctrl@02B40000 { compatible = "qcom,slpi-pinctrl"; reg = <0x2B40000 0x20000>; qcom,num-pins = <14>; status = "disabled"; qupv3_se20_i2c_pins: qupv3_se20_i2c_pins { qupv3_se20_i2c_active: qupv3_se20_i2c_active { mux { pins = "gpio0", "gpio1"; function = "func1"; }; config { pins = "gpio0", "gpio1"; drive-strength = <2>; bias-disable; }; }; qupv3_se20_i2c_sleep: qupv3_se20_i2c_sleep { mux { pins = "gpio0", "gpio1"; function = "gpio"; }; config { pins = "gpio0", "gpio1"; drive-strength = <2>; bias-pull-down; }; }; }; qupv3_se21_i2c_pins: qupv3_se21_i2c_pins { qupv3_se21_i2c_active: qupv3_se21_i2c_active { mux { pins = "gpi2", "gpio3"; function = "func1"; }; config { pins = "gpio2", "gpio3"; drive-strength = <2>; bias-disable; }; }; qupv3_se21_i2c_sleep: qupv3_se21_i2c_sleep { mux { pins = "gpio2", "gpio3"; function = "gpio"; }; config { pins = "gpio2", "gpio3"; drive-strength = <2>; bias-pull-down; }; }; }; qupv3_se22_i2c_pins: qupv3_se22_i2c_pins { qupv3_se22_i2c_active: qupv3_se22_i2c_active { mux { pins = "gpio6", "gpio7"; function = "func1"; }; config { pins = "gpio6", "gpio7"; drive-strength = <2>; bias-disable; }; }; qupv3_se22_i2c_sleep: qupv3_se22_i2c_sleep { mux { pins = "gpio6", "gpio7"; function = "gpio"; }; config { pins = "gpio6", "gpio7"; drive-strength = <2>; bias-pull-down; }; }; }; qupv3_se23_i2c_pins: qupv3_se23_i2c_pins { qupv3_se23_i2c_active: qupv3_se23_i2c_active { mux { pins = "gpio8", "gpio9"; function = "func3"; }; config { pins = "gpio8", "gpio9"; drive-strength = <2>; bias-disable; }; }; qupv3_se23_i2c_sleep: qupv3_se23_i2c_sleep { mux { pins = "gpio8", "gpio9"; function = "gpio"; }; config { pins = "gpio8", "gpio9"; drive-strength = <2>; bias-pull-down; }; }; }; /* SE21 pin mappings */ qupv3_se21_spi_pins: qupv3_se21_spi_pins { qupv3_se21_spi_active: qupv3_se21_spi_active { mux { pins = "gpio2", "gpio3", "gpio4", "gpio5"; function = "func1"; }; config { pins = "gpio2", "gpio3", "gpio4", "gpio5"; drive-strength = <6>; bias-disable; }; }; qupv3_se21_spi_sleep: qupv3_se21_spi_sleep { mux { pins = "gpio2", "gpio3", "gpio4", "gpio5"; function = "gpio"; }; config { pins = "gpio2", "gpio3", "gpio4", "gpio5"; drive-strength = <2>; bias-pull-down; }; }; }; /*SE22 pin mappings*/ qupv3_se22_spi_pins: qupv3_se22_spi_pins { qupv3_se22_spi_active: qupv3_se22_spi_active { mux { pins = "gpio6", "gpio7", "gpio8", "gpio9"; function = "func1"; }; config { pins = "gpio6", "gpio7", "gpio8", "gpio9"; drive-strength = <6>; bias-disable; }; }; qupv3_se22_spi_sleep: qupv3_se22_spi_sleep { mux { pins = "gpio6", "gpio7", "gpio8", "gpio9"; function = "gpio"; }; config { pins = "gpio6", "gpio7", "gpio8", "gpio9"; drive-strength = <2>; bias-pull-down; }; }; }; }; }; qcom/sm8150.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -752,3 +752,4 @@ #include "sm8150-pinctrl.dtsi" #include "sm8150-regulator.dtsi" #include "sm8150-pm.dtsi" #include "sm8150-slpi-pinctrl.dtsi" Loading
bindings/pinctrl/qcom,slpi-pinctrl.txt 0 → 100644 +123 −0 Original line number Diff line number Diff line Qualcomm Technologies, Inc. SLPI Pin controller driver This DT bindings describes the Pin controller driver being added for supporting SLPI (Sensor Low Power Island) TLMM from QTI chipsets. Following properties are for SLPI Pin controller device main node. - compatible: Usage: required Value type: <string> Definition: must be "qcom,slpi-pinctrl" - reg: Usage: required Value type: <prop-encoded-array> Definition: Base address and size of the SLPI TLMM register space. - qcom,num-pins: Usage: required Value type: <u32> Definition: Number of PINs supported by the SLPI TLMM. Please refer to pinctrl-bindings.txt in this directory for details of the common pinctrl bindings used by client devices, including the meaning of the phrase "pin configuration node". The pin configuration nodes act as a container for an arbitrary number of subnodes. Each of these subnodes represents some desired configuration for a pin or a list of pins. This configuration can include the mux function to select on those pin(s), and various pin configuration parameters, as listed below. SUBNODES: The name of each subnode is not important; all subnodes should be enumerated and processed purely based on their content. Each subnode only affects those parameters that are explicitly listed. In other words, a subnode that lists a mux function but no pin configuration parameters implies no information about any pin configuration parameters. Similarly, a pin subnode that describes a pullup parameter implies no information about e.g. the mux function. The following generic properties as defined in pinctrl-bindings.txt are valid to specify in a pin configuration subnode: - pins: Usage: required Value type: <string-array> Definition: List of gpio pins affected by the properties specified in this subnode. Valid pins are: gpio0-gpio31 for LPI. - function: Usage: required Value type: <string> Definition: Specify the alternative function to be configured for the specified pins. Valid values are: "gpio", "func1", "func2", "func3", "func4", "func5" - bias-disable: Usage: optional Value type: <none> Definition: The specified pins should be configured as no pull. - bias-pull-down: Usage: optional Value type: <none> Definition: The specified pins should be configured as pull down. - bias-bus-hold: Usage: optional Value type: <none> Definition: The specified pins should be configured as bus-keeper mode. - bias-pull-up: Usage: optional Value type: <empty> Definition: The specified pins should be configured as pull up. - qcom,drive-strength: Usage: optional Value type: <u32> Definition: Selects the drive strength for the specified pins. Example: slpi_tlmm: slpi_pinctrl@02b40000 { compatible = "qcom,slpi-pinctrl"; qcom,num-pins = <14>; reg = <0x02b40000 0x20000>; slpi_mclk0_active: slpi_mclk0_active { mux { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "func2"; }; config { pins = "gpio0", "gpio1", "gpio2", "gpio3"; drive-strength = <8>; bias-disable; }; }; slpi_mclk0_sleep: slpi_mclk0_sleep { mux { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "func2"; }; config { pins = "gpio0", "gpio1", "gpio2", "gpio3"; drive-strength = <2>; bias-pull-down; }; }; };
qcom/sa8155.dtsi +4 −0 Original line number Diff line number Diff line Loading @@ -49,5 +49,9 @@ /delete-node/ rpmh-regulator-ldof6; }; &slpi_tlmm { status = "ok"; }; /* Add regulator nodes specific to SA8155 */ #include "sa8155-regulator.dtsi"
qcom/sm8150-slpi-pinctrl.dtsi 0 → 100644 +186 −0 Original line number Diff line number Diff line &soc { slpi_tlmm: slpi_pinctrl@02B40000 { compatible = "qcom,slpi-pinctrl"; reg = <0x2B40000 0x20000>; qcom,num-pins = <14>; status = "disabled"; qupv3_se20_i2c_pins: qupv3_se20_i2c_pins { qupv3_se20_i2c_active: qupv3_se20_i2c_active { mux { pins = "gpio0", "gpio1"; function = "func1"; }; config { pins = "gpio0", "gpio1"; drive-strength = <2>; bias-disable; }; }; qupv3_se20_i2c_sleep: qupv3_se20_i2c_sleep { mux { pins = "gpio0", "gpio1"; function = "gpio"; }; config { pins = "gpio0", "gpio1"; drive-strength = <2>; bias-pull-down; }; }; }; qupv3_se21_i2c_pins: qupv3_se21_i2c_pins { qupv3_se21_i2c_active: qupv3_se21_i2c_active { mux { pins = "gpi2", "gpio3"; function = "func1"; }; config { pins = "gpio2", "gpio3"; drive-strength = <2>; bias-disable; }; }; qupv3_se21_i2c_sleep: qupv3_se21_i2c_sleep { mux { pins = "gpio2", "gpio3"; function = "gpio"; }; config { pins = "gpio2", "gpio3"; drive-strength = <2>; bias-pull-down; }; }; }; qupv3_se22_i2c_pins: qupv3_se22_i2c_pins { qupv3_se22_i2c_active: qupv3_se22_i2c_active { mux { pins = "gpio6", "gpio7"; function = "func1"; }; config { pins = "gpio6", "gpio7"; drive-strength = <2>; bias-disable; }; }; qupv3_se22_i2c_sleep: qupv3_se22_i2c_sleep { mux { pins = "gpio6", "gpio7"; function = "gpio"; }; config { pins = "gpio6", "gpio7"; drive-strength = <2>; bias-pull-down; }; }; }; qupv3_se23_i2c_pins: qupv3_se23_i2c_pins { qupv3_se23_i2c_active: qupv3_se23_i2c_active { mux { pins = "gpio8", "gpio9"; function = "func3"; }; config { pins = "gpio8", "gpio9"; drive-strength = <2>; bias-disable; }; }; qupv3_se23_i2c_sleep: qupv3_se23_i2c_sleep { mux { pins = "gpio8", "gpio9"; function = "gpio"; }; config { pins = "gpio8", "gpio9"; drive-strength = <2>; bias-pull-down; }; }; }; /* SE21 pin mappings */ qupv3_se21_spi_pins: qupv3_se21_spi_pins { qupv3_se21_spi_active: qupv3_se21_spi_active { mux { pins = "gpio2", "gpio3", "gpio4", "gpio5"; function = "func1"; }; config { pins = "gpio2", "gpio3", "gpio4", "gpio5"; drive-strength = <6>; bias-disable; }; }; qupv3_se21_spi_sleep: qupv3_se21_spi_sleep { mux { pins = "gpio2", "gpio3", "gpio4", "gpio5"; function = "gpio"; }; config { pins = "gpio2", "gpio3", "gpio4", "gpio5"; drive-strength = <2>; bias-pull-down; }; }; }; /*SE22 pin mappings*/ qupv3_se22_spi_pins: qupv3_se22_spi_pins { qupv3_se22_spi_active: qupv3_se22_spi_active { mux { pins = "gpio6", "gpio7", "gpio8", "gpio9"; function = "func1"; }; config { pins = "gpio6", "gpio7", "gpio8", "gpio9"; drive-strength = <6>; bias-disable; }; }; qupv3_se22_spi_sleep: qupv3_se22_spi_sleep { mux { pins = "gpio6", "gpio7", "gpio8", "gpio9"; function = "gpio"; }; config { pins = "gpio6", "gpio7", "gpio8", "gpio9"; drive-strength = <2>; bias-pull-down; }; }; }; }; };
qcom/sm8150.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -752,3 +752,4 @@ #include "sm8150-pinctrl.dtsi" #include "sm8150-regulator.dtsi" #include "sm8150-pm.dtsi" #include "sm8150-slpi-pinctrl.dtsi"
