Merge 62206deed6e638dca8afffaf9656a73b56fd849f on remote branch (9ac84ff4) · Commits · e / devices / android_kernel_fairphone_FP5

fw/htt.h

+173 −1

Original line number	Diff line number	Diff line
		@@ -211,9 +211,10 @@
		* 3.87 Add on-chip AST index field to PEER_MAP_V2 msg.
		* 3.88 Add HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE def.
		* 3.89 Add MSDU queue enumerations.
		* 3.90 Add HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND def.
		*/
		#define HTT_CURRENT_VERSION_MAJOR 3
		#define HTT_CURRENT_VERSION_MINOR 89
		#define HTT_CURRENT_VERSION_MINOR 90

		#define HTT_NUM_TX_FRAG_DESC 1024

		@@ -7050,6 +7051,7 @@ enum htt_t2h_msg_type {
		HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND = 0x25,
		HTT_T2H_MSG_TYPE_CHAN_CALDATA = 0x26,
		HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND = 0x27,
		HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28,


		HTT_T2H_MSG_TYPE_TEST,
		@@ -14598,4 +14600,174 @@ enum HTT_MSDUQ_LEGACY_FLOW_INDEX {
		HTT_MSDUQ_LEGACY_NON_UDP_FLOW_INDEX = 3,
		};

		/**
		* @brief target -> host mlo timestamp offset indication
		*
		* MSG_TYPE => HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND
		*
		* @details
		* The following field definitions describe the format of the HTT target
		* to host mlo timestamp offset indication message.
		*
		*
		* \|31 16\|15 12\|11 10\|9 8\|7 0 \|
		* \|----------------------------------------------------------------------\|
		* \| mac_clk_freq_mhz \| rsvd \|chip_id\|pdev_id\| msg type \|
		* \|----------------------------------------------------------------------\|
		* \| Sync time stamp lo in us \|
		* \|----------------------------------------------------------------------\|
		* \| Sync time stamp hi in us \|
		* \|----------------------------------------------------------------------\|
		* \| mlo time stamp offset lo in us \|
		* \|----------------------------------------------------------------------\|
		* \| mlo time stamp offset hi in us \|
		* \|----------------------------------------------------------------------\|
		* \| mlo time stamp offset clocks in clock ticks \|
		* \|----------------------------------------------------------------------\|
		* \|31 26\|25 16\|15 0 \|
		* \|rsvd2 \| mlo time stamp \| mlo time stamp compensation in us \|
		* \| \| compensation in clks \| \|
		* \|----------------------------------------------------------------------\|
		* \|31 22\|21 0 \|
		* \| rsvd 3 \| mlo time stamp comp timer period \|
		* \|----------------------------------------------------------------------\|
		* The message is interpreted as follows:
		*
		* dword0 - b'0:7 - msg_type: This will be set to
		* HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND
		* value: 0x28
		*
		* dword0 - b'9:8 - pdev_id
		*
		* dword0 - b'11:10 - chip_id
		*
		* dword0 - b'15:12 - rsvd1: Reserved for future use
		*
		* dword0 - b'31:16 - mac clock frequency of the mac HW block in MHz
		*
		* dword1 - b'31:0 - lower 32 bits of the WLAN global time stamp (in us) at
		* which last sync interrupt was received
		*
		* dword2 - b'31:0 - upper 32 bits of the WLAN global time stamp (in us) at
		* which last sync interrupt was received
		*
		* dword3 - b'31:0 - lower 32 bits of the MLO time stamp offset in us
		*
		* dword4 - b'31:0 - upper 32 bits of the MLO time stamp offset in us
		*
		* dword5 - b'31:0 - MLO time stamp offset in clock ticks for sub us
		*
		* dword6 - b'15:0 - MLO time stamp compensation applied in us
		*
		* dword6 - b'25:16 - MLO time stamp compensation applied in clock ticks
		* for sub us resolution
		*
		* dword6 - b'31:26 - rsvd2: Reserved for future use
		*
		* dword7 - b'21:0 - period of MLO compensation timer at which compensation
		* is applied, in us
		*
		* dword7 - b'31:22 - rsvd3: Reserved for future use
		*/

		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_M 0x000000FF
		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_S 0

		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_M 0x00000300
		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_S 8

		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_M 0x00000C00
		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_S 10

		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_M 0xFFFF0000
		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_S 16

		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_M 0x0000FFFF
		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_S 0

		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_M 0x03FF0000
		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_S 16

		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_M 0x003FFFFF
		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_S 0

		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_GET(_var) \
		(((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_M) >> HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_S)
		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE, _val); \
		((_var) \|= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_S)); \
		} while (0)

		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_GET(_var) \
		(((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_M) >> HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_S)
		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID, _val); \
		((_var) \|= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_S)); \
		} while (0)

		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_GET(_var) \
		(((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_M) >> HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_S)
		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID, _val); \
		((_var) \|= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_S)); \
		} while (0)

		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_GET(_var) \
		(((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_M) >> \
		HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_S)
		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ, _val); \
		((_var) \|= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_S)); \
		} while (0)

		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_GET(_var) \
		(((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_M) >> \
		HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_S)
		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US, _val); \
		((_var) \|= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_S)); \
		} while (0)

		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_GET(_var) \
		(((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_M) >> \
		HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_S)
		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS, _val); \
		((_var) \|= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_S)); \
		} while (0)

		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_GET(_var) \
		(((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_M) >> \
		HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_S)
		#define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US, _val); \
		((_var) \|= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_S)); \
		} while (0)

		typedef struct {
		A_UINT32 msg_type: 8, /* bits 7:0 */
		pdev_id: 2, /* bits 9:8 */
		chip_id: 2, /* bits 11:10 */
		reserved1: 4, /* bits 15:12 */
		mac_clk_freq_mhz: 16; /* bits 31:16 */
		A_UINT32 sync_timestamp_lo_us;
		A_UINT32 sync_timestamp_hi_us;
		A_UINT32 mlo_timestamp_offset_lo_us;
		A_UINT32 mlo_timestamp_offset_hi_us;
		A_UINT32 mlo_timestamp_offset_clks;
		A_UINT32 mlo_timestamp_comp_us: 16, /* bits 15:0 */
		mlo_timestamp_comp_clks: 10, /* bits 25:16 */
		reserved2: 6; /* bits 31:26 */
		A_UINT32 mlo_timestamp_comp_timer_period_us: 22, /* bits 21:0 */
		reserved3: 10; /* bits 31:22 */
		} htt_t2h_mlo_offset_ind_t;


		#endif

fw/htt_stats.h

+25 −0

Original line number	Diff line number	Diff line
		@@ -2748,6 +2748,25 @@ typedef struct {
		A_UINT32 q_empty_failure;
		A_UINT32 q_not_empty_failure;
		A_UINT32 add_msdu_failure;

		/* TQM reset debug stats */
		A_UINT32 tqm_cache_ctl_err;
		A_UINT32 tqm_soft_reset;
		A_UINT32 tqm_reset_total_num_in_use_link_descs;
		A_UINT32 tqm_reset_worst_case_num_lost_link_descs;
		A_UINT32 tqm_reset_worst_case_num_lost_host_tx_bufs_count;
		A_UINT32 tqm_reset_num_in_use_link_descs_internal_tqm;
		A_UINT32 tqm_reset_num_in_use_link_descs_wbm_idle_link_ring;
		A_UINT32 tqm_reset_time_to_tqm_hang_delta_ms;
		A_UINT32 tqm_reset_recovery_time_ms;
		A_UINT32 tqm_reset_num_peers_hdl;
		A_UINT32 tqm_reset_cumm_dirty_hw_mpduq_proc_cnt;
		A_UINT32 tqm_reset_cumm_dirty_hw_msduq_proc;
		A_UINT32 tqm_reset_flush_cache_cmd_su_cnt;
		A_UINT32 tqm_reset_flush_cache_cmd_other_cnt;
		A_UINT32 tqm_reset_flush_cache_cmd_trig_type;
		A_UINT32 tqm_reset_flush_cache_cmd_trig_cfg;
		A_UINT32 tqm_reset_flush_cache_cmd_skip_cmd_status_null;
		} htt_tx_tqm_error_stats_tlv;

		/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TQM
		@@ -5633,6 +5652,12 @@ typedef struct {
		* 0-disabled, 1-enabled
		*/
		A_UINT32 dyn_cca_status;
		/* RXDEAF Register value
		* rxdesense_thresh_sw - VREG Register
		* rxdesense_thresh_hw - PHY Register
		*/
		A_UINT32 rxdesense_thresh_sw;
		A_UINT32 rxdesense_thresh_hw;
		} htt_phy_reset_stats_tlv;

		typedef struct {

fw/wlan_defs.h

+259 −0

Original line number	Diff line number	Diff line
		@@ -1295,4 +1295,263 @@ typedef enum {
		#undef CONFIG_160MHZ_SUPPORT_UNDEF_WAR
		#endif

		/** MGMT RX REO Changes */
		/* Macros for having versioning info for compatibility check between host and firmware */
		#define MLO_SHMEM_MAJOR_VERSION 1
		#define MLO_SHMEM_MINOR_VERSION 1

		/** Helper Macros for tlv header of the given tlv buffer */
		/* Size of the TLV Header which is the Tag and Length fields */
		#define MLO_SHMEM_TLV_HDR_SIZE (1 * sizeof(A_UINT32))

		/* TLV Helper macro to get the TLV Header given the pointer to the TLV buffer. */
		#define MLO_SHMEMTLV_GET_HDR(tlv_buf) (((A_UINT32 *) (tlv_buf))[0])

		/* TLV Helper macro to set the TLV Header given the pointer to the TLV buffer. */
		#define MLO_SHMEMTLV_SET_HDR(tlv_buf, tag, len) \
		(((A_UINT32 *)(tlv_buf))[0]) = ((tag << 16) \| (len & 0x0000FFFF))

		/* TLV Helper macro to get the TLV Tag given the TLV header. */
		#define MLO_SHMEMTLV_GET_TLVTAG(tlv_header) ((A_UINT32)((tlv_header) >> 16))

		/*
		* TLV Helper macro to get the TLV Buffer Length (minus TLV header size)
		* given the TLV header.
		*/
		#define MLO_SHMEMTLV_GET_TLVLEN(tlv_header) \
		((A_UINT32)((tlv_header) & 0x0000FFFF))

		/*
		* TLV Helper macro to get the TLV length from TLV structure size
		* by removing TLV header size.
		*/
		#define MLO_SHMEMTLV_GET_STRUCT_TLVLEN(tlv_struct) \
		((A_UINT32)(sizeof(tlv_struct)-MLO_SHMEM_TLV_HDR_SIZE))

		/**
		* Helper Macros for getting and setting the required number of bits
		* from the TLV params.
		*/
		#define MLO_SHMEM_GET_BITS(_val,_index,_num_bits) \
		(((_val) >> (_index)) & ((1 << (_num_bits)) - 1))

		#define MLO_SHMEM_SET_BITS(_var,_index,_num_bits,_val) \
		do { \
		(_var) &= ~(((1 << (_num_bits)) - 1) << (_index)); \
		(_var) \|= (((_val) & ((1 << (_num_bits)) - 1)) << (_index)); \
		} while (0)

		/** Definition of the GLB_H_SHMEM arena tlv structures */

		typedef enum {
		MLO_SHMEM_TLV_STRUCT_MGMT_RX_REO_SNAPSHOT,
		MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_PER_LINK_SNAPSHOT_INFO,
		MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_SNAPSHOT_INFO,
		MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK,
		MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK_INFO,
		MLO_SHMEM_TLV_STRUCT_MLO_GLB_H_SHMEM,
		} MLO_SHMEM_TLV_TAG_ID;

		/** Helper macro for params GET/SET of mgmt_rx_reo_snapshot */
		#define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_VALID_GET(mgmt_rx_reo_snapshot_low) MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 0, 1)
		#define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_VALID_SET(mgmt_rx_reo_snapshot_low, value) MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot_low, 0, 1, value)

		#define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_MGMT_PKT_CTR_GET(mgmt_rx_reo_snapshot_low) MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 1, 16)
		#define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_MGMT_PKT_CTR_SET(mgmt_rx_reo_snapshot_low, value) MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot_low, 1, 16, value)

		#define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_GLOBAL_TIMESTAMP_GET(mgmt_rx_reo_snapshot) \
		(MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot->mgmt_rx_reo_snapshot_high, 0, 17) << 15) \| \
		MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot->mgmt_rx_reo_snapshot_low, 17, 15)

		#define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_GLOBAL_TIMESTAMP_SET(mgmt_rx_reo_snapshot, value) \
		do { \
		MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot->mgmt_rx_reo_snapshot_high, 0, 17, ((value) >> 15)); \
		MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot->mgmt_rx_reo_snapshot_low, 17, 15, ((value) & 0x7fff)); \
		} while (0)

		#define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_MGMT_PKT_CTR_REDUNDANT_GET(mgmt_rx_reo_snapshot_high) MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_high, 17, 15)
		#define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_MGMT_PKT_CTR_REDUNDANT_SET(mgmt_rx_reo_snapshot_high, value) MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot_high, 17, 15, value)

		#define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_IS_CONSISTENT(mgmt_pkt_ctr, mgmt_pkt_ctr_redundant) \
		(MLO_SHMEM_GET_BITS(mgmt_pkt_ctr, 0, 15) == MLO_SHMEM_GET_BITS(mgmt_pkt_ctr_redundant, 0, 15))

		#define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_GLOBAL_TIMESTAMP_GET_FROM_DWORDS(mgmt_rx_reo_snapshot_low,mgmt_rx_reo_snapshot_high) \
		(MLO_SHMEM_GET_BITS((mgmt_rx_reo_snapshot_high), 0, 17) << 15) \| \
		MLO_SHMEM_GET_BITS((mgmt_rx_reo_snapshot_low), 17, 15)

		#define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GET_ADRESS(mgmt_rx_reo_snapshot) \
		(&mgmt_rx_reo_snapshot->mgmt_rx_reo_snapshot_low)

		/* REO snapshot structure */
		typedef struct {
		/* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MGMT_RX_REO_SNAPSHOT */
		A_UINT32 tlv_header;
		A_UINT32 reserved_alignment_padding;
		/**
		* mgmt_rx_reo_snapshot_low
		*
		* [0]: valid
		* [16:1]: mgmt_pkt_ctr
		* [31:17]: global_timestamp_low
		*/
		A_UINT32 mgmt_rx_reo_snapshot_low;

		/**
		* mgmt_rx_reo_snapshot_high
		*
		* [16:0]: global_timestamp_high
		* [31:17]: mgmt_pkt_ctr_redundant
		*/
		A_UINT32 mgmt_rx_reo_snapshot_high;

		} mgmt_rx_reo_snapshot;

		A_COMPILE_TIME_ASSERT(check_mgmt_rx_reo_snapshot_8byte_size_quantum,
		(((sizeof(mgmt_rx_reo_snapshot) % sizeof(A_UINT64) == 0x0))));

		A_COMPILE_TIME_ASSERT(verify_mgmt_rx_reo_snapshot_low_offset,
		(A_OFFSETOF(mgmt_rx_reo_snapshot, mgmt_rx_reo_snapshot_low) % sizeof(A_UINT64) == 0));

		typedef struct {
		/* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_PER_LINK_SNAPSHOT_INFO */
		A_UINT32 tlv_header;
		A_UINT32 reserved_alignment_padding;
		mgmt_rx_reo_snapshot fw_consumed;
		mgmt_rx_reo_snapshot fw_forwarded;
		mgmt_rx_reo_snapshot hw_forwarded;
		} mlo_glb_rx_reo_per_link_snapshot_info;

		A_COMPILE_TIME_ASSERT(check_mlo_glb_rx_reo_per_link_snapshot_info_8byte_size_quantum,
		(((sizeof(mlo_glb_rx_reo_per_link_snapshot_info) % sizeof(A_UINT64) == 0x0))));

		A_COMPILE_TIME_ASSERT(verify_mlo_glb_rx_reo_per_link_snapshot_fw_consumed_offset,
		(A_OFFSETOF(mlo_glb_rx_reo_per_link_snapshot_info, fw_consumed) % sizeof(A_UINT64) == 0));

		/** Helper macro for params GET/SET of mlo_glb_rx_reo_snapshot_info */
		#define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_NO_OF_LINKS_GET(link_info) MLO_SHMEM_GET_BITS(link_info, 0, 4)
		#define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_NO_OF_LINKS_SET(link_info, value) MLO_SHMEM_SET_BITS(link_info, 0, 4, value)

		#define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_VALID_LINK_BMAP_GET(link_info) MLO_SHMEM_GET_BITS(link_info, 4, 16)
		#define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_VALID_LINK_BMAP_SET(link_info, value) MLO_SHMEM_SET_BITS(link_info, 4, 16, value)

		/* Definition of the complete REO snapshot info */
		typedef struct {
		/* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_SNAPSHOT_INFO */
		A_UINT32 tlv_header;

		/**
		* link_info
		*
		* [3:0]: no_of_links
		* [19:4]: valid_link_bmap
		* [31:20]: reserved
		*/
		A_UINT32 link_info;
		/* This TLV is followed by array of mlo_glb_rx_reo_per_link_snapshot_info:
		* mlo_glb_rx_reo_per_link_snapshot_info will have multiple instances
		* equal to num of hw links received by no_of_link
		* mlo_glb_rx_reo_per_link_snapshot_info per_link_info[];
		*/
		} mlo_glb_rx_reo_snapshot_info;

		A_COMPILE_TIME_ASSERT(check_mlo_glb_rx_reo_snapshot_info_8byte_size_quantum,
		(((sizeof(mlo_glb_rx_reo_snapshot_info) % sizeof(A_UINT64) == 0x0))));

		/** Helper macro for params GET/SET of mlo_glb_link */
		#define MLO_SHMEM_GLB_LINK_PARAM_LINK_STATUS_GET(link_status) MLO_SHMEM_GET_BITS(link_status, 0, 8)
		#define MLO_SHMEM_GLB_LINK_PARAM_LINK_STATUS_SET(link_status, value) MLO_SHMEM_SET_BITS(link_status, 0, 8, value)

		/glb link info structures used for scratchpad memory (crash and recovery) /
		typedef struct {
		/* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK */
		A_UINT32 tlv_header;
		/**
		* link_status
		*
		* [7:0]: link_status
		* [31:8]: reserved
		*/
		A_UINT32 link_status;
		/*
		* Based on MLO timestamp, which is global across chips -
		* this will be first updated when MLO sync is completed.
		*/
		A_UINT32 boot_timestamp_low_us;
		A_UINT32 boot_timestamp_high_us;
		/*
		* Based on MLO timestamp, will be updated with a configurable
		* periodicity (default 1 sec)
		*/
		A_UINT32 health_check_timestamp_low_us;
		A_UINT32 health_check_timestamp_high_us;

		} mlo_glb_link;

		A_COMPILE_TIME_ASSERT(check_mlo_glb_link_8byte_size_quantum,
		(((sizeof(mlo_glb_link) % sizeof(A_UINT64) == 0x0))));

		A_COMPILE_TIME_ASSERT(verify_mlo_glb_link_boot_timestamp_low_offset,
		(A_OFFSETOF(mlo_glb_link, boot_timestamp_low_us) % sizeof(A_UINT64) == 0));

		A_COMPILE_TIME_ASSERT(verify_mlo_glb_link_health_check_timestamp_low_offset,
		(A_OFFSETOF(mlo_glb_link, health_check_timestamp_low_us) % sizeof(A_UINT64) == 0));


		/** Helper macro for params GET/SET of mlo_glb_link_info */
		#define MLO_SHMEM_GLB_LINK_INFO_PARAM_NO_OF_LINKS_GET(link_info) MLO_SHMEM_GET_BITS(link_info, 0, 4)
		#define MLO_SHMEM_GLB_LINK_INFO_PARAM_NO_OF_LINKS_SET(link_info, value) MLO_SHMEM_SET_BITS(link_info, 0, 4, value)

		#define MLO_SHMEM_GLB_LINK_INFO_PARAM_VALID_LINK_BMAP_GET(link_info) MLO_SHMEM_GET_BITS(link_info, 4, 16)
		#define MLO_SHMEM_GLB_LINK_INFO_PARAM_VALID_LINK_BMAP_SET(link_info, value) MLO_SHMEM_SET_BITS(link_info, 4, 16, value)

		typedef struct {
		/* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK_INFO */
		A_UINT32 tlv_header;

		/**
		* link_info
		*
		* [3:0]: no_of_links
		* [19:4]: valid_link_bmap
		* [31:20]: reserved
		*/
		A_UINT32 link_info;
		/* This TLV is followed by array of mlo_glb_link:
		* mlo_glb_link will have mutiple instances equal to num of hw links
		* received by no_of_link
		* mlo_glb_link glb_link_info[];
		*/
		} mlo_glb_link_info;

		A_COMPILE_TIME_ASSERT(check_mlo_glb_link_info_8byte_size_quantum,
		(((sizeof(mlo_glb_link_info) % sizeof(A_UINT64) == 0x0))));

		/** Helper macro for params GET/SET of mlo_glb_h_shmem */
		#define MLO_SHMEM_GLB_H_SHMEM_PARAM_MINOR_VERSION_GET(major_minor_version) MLO_SHMEM_GET_BITS(major_minor_version, 0, 16)
		#define MLO_SHMEM_GLB_H_SHMEM_PARAM_MINOR_VERSION_SET(major_minor_version, value) MLO_SHMEM_SET_BITS(major_minor_version, 0, 16, value)

		#define MLO_SHMEM_GLB_H_SHMEM_PARAM_MAJOR_VERSION_GET(major_minor_version) MLO_SHMEM_GET_BITS(major_minor_version, 16, 16)
		#define MLO_SHMEM_GLB_H_SHMEM_PARAM_MAJOR_VERSION_SET(major_minor_version, value) MLO_SHMEM_SET_BITS(major_minor_version, 16, 16, value)

		/* Definition of Global H SHMEM Arena */
		typedef struct {
		/* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_H_SHMEM */
		A_UINT32 tlv_header;
		/**
		* major_minor_version
		*
		* [15:0]: minor version
		* [31:16]: major version
		*/
		A_UINT32 major_minor_version;
		/* This TLV is followed by TLVs
		* mlo_glb_rx_reo_snapshot_info reo_snapshot;
		* mlo_glb_link_info glb_info;
		*/
		} mlo_glb_h_shmem;

		A_COMPILE_TIME_ASSERT(check_mlo_glb_h_shmem_8byte_size_quantum,
		(((sizeof(mlo_glb_h_shmem) % sizeof(A_UINT64) == 0x0))));


		#endif /* __WLANDEFS_H__ */

fw/wmi_services.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -534,6 +534,10 @@ typedef enum {
		WMI_SERVICE_11BE = 289, /* Indicates FW supports 11be */
		WMI_SERVICE_BIG_DATA_SUPPORT = 290, /* Indicates FW supports Big Data feature */
		WMI_SERVICE_EAPOL_OVER_NWIFI = 291, /* Indicates FW supports sending eapol frames in native wifi mode even when the vdev is brought up in raw ethernet mode */
		WMI_SERVICE_AMPDU_TX_BUF_SIZE_256_SUPPORT = 292, /* Indicates FW supports MAX 256 MPDUs in A-MPDU instead of 64 */
		WMI_SERVICE_HALPHY_CAL_STATUS = 293, /* Indicates FW supports sending online HALPHY Calibration status to host */
		WMI_SERVICE_HALPHY_CAL_ENABLE_DISABLE_SUPPORT = 294, /* Indicates Calibraton enable/disable support by FW */
		WMI_SERVICE_AFC_SUPPORT = 295, /* Indicates FW supports AFC_CMD,AFC_EVENT */


		WMI_MAX_EXT2_SERVICE

fw/wmi_tlv_defs.h

+84 −2

File changed.

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