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Commit 9a900eca authored by Don Skidmore's avatar Don Skidmore Committed by Jeff Kirsher
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ixgbe: add array of MAC type dependent values 



Some of the register addresses and format where unfortunately changed
between MAC types. To get around this we add a const u32 *mvals pointer
to the ixgbe_hw struct to point to an array of mac-type-dependent
values.  These can include register offsets, masks, whatever can be in
a u32. When the ixgbe_hw struct is initialized, a pointer to the
appropriate array must be set.

Signed-off-by: default avatarDon Skidmore <donald.c.skidmore@intel.com>
Tested-by: default avatarPhil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 6651ee07

drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c

+1 −0
Original line number Diff line number Diff line
@@ -1234,4 +1234,5 @@ struct ixgbe_info ixgbe_82598_info = { 
	.mac_ops		= &mac_ops_82598,

	.eeprom_ops		= &eeprom_ops_82598,

	.phy_ops		= &phy_ops_82598,

	.mvals			= ixgbe_mvals_8259X,

};

drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c

+4 −3
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 
{

	u32 fwsm, manc, factps;



	fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);

	fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));

	if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)

		return false;
@@ -79,7 +79,7 @@ bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 
	if (!(manc & IXGBE_MANC_RCV_TCO_EN))

		return false;



	factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);

	factps = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw));

	if (factps & IXGBE_FACTPS_MNGCG)

		return false;
@@ -510,7 +510,7 @@ static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) 
	hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);



	/* Check to see if MNG FW could be enabled */

	fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);

	fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));



	if (((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) &&

	    !hw->wol_enabled &&
@@ -2378,4 +2378,5 @@ struct ixgbe_info ixgbe_82599_info = { 
	.eeprom_ops             = &eeprom_ops_82599,

	.phy_ops                = &phy_ops_82599,

	.mbx_ops                = &mbx_ops_generic,

	.mvals			= ixgbe_mvals_8259X,

};

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

+32 −27
Original line number Diff line number Diff line
@@ -57,6 +57,11 @@ static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 
						 u16 offset);

static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);



/* Base table for registers values that change by MAC */

const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = {

	IXGBE_MVALS_INIT(8259X)

};



/**

 *  ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow

 *  control
@@ -681,7 +686,7 @@ void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 
	bus->lan_id = bus->func;



	/* check for a port swap */

	reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);

	reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw));

	if (reg & IXGBE_FACTPS_LFS)

		bus->func ^= 0x1;

}
@@ -799,7 +804,7 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 
		 * Check for EEPROM present first.

		 * If not present leave as none

		 */

		eec = IXGBE_READ_REG(hw, IXGBE_EEC);

		eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));

		if (eec & IXGBE_EEC_PRES) {

			eeprom->type = ixgbe_eeprom_spi;
@@ -1283,14 +1288,14 @@ static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 
	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)

		return IXGBE_ERR_SWFW_SYNC;



	eec = IXGBE_READ_REG(hw, IXGBE_EEC);

	eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));



	/* Request EEPROM Access */

	eec |= IXGBE_EEC_REQ;

	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);

	IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);



	for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {

		eec = IXGBE_READ_REG(hw, IXGBE_EEC);

		eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));

		if (eec & IXGBE_EEC_GNT)

			break;

		udelay(5);
@@ -1299,7 +1304,7 @@ static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 
	/* Release if grant not acquired */

	if (!(eec & IXGBE_EEC_GNT)) {

		eec &= ~IXGBE_EEC_REQ;

		IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);

		IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);

		hw_dbg(hw, "Could not acquire EEPROM grant\n");



		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
@@ -1309,7 +1314,7 @@ static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 
	/* Setup EEPROM for Read/Write */

	/* Clear CS and SK */

	eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);

	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);

	IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);

	IXGBE_WRITE_FLUSH(hw);

	udelay(1);

	return 0;
@@ -1333,7 +1338,7 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 
		 * If the SMBI bit is 0 when we read it, then the bit will be

		 * set and we have the semaphore

		 */

		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);

		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));

		if (!(swsm & IXGBE_SWSM_SMBI))

			break;

		usleep_range(50, 100);
@@ -1353,7 +1358,7 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 
		 * If the SMBI bit is 0 when we read it, then the bit will be

		 * set and we have the semaphore

		 */

		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);

		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));

		if (swsm & IXGBE_SWSM_SMBI) {

			hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n");

			return IXGBE_ERR_EEPROM;
@@ -1362,16 +1367,16 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 


	/* Now get the semaphore between SW/FW through the SWESMBI bit */

	for (i = 0; i < timeout; i++) {

		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);

		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));



		/* Set the SW EEPROM semaphore bit to request access */

		swsm |= IXGBE_SWSM_SWESMBI;

		IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);

		IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);



		/* If we set the bit successfully then we got the

		 * semaphore.

		 */

		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);

		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));

		if (swsm & IXGBE_SWSM_SWESMBI)

			break;
@@ -1400,11 +1405,11 @@ static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 
{

	u32 swsm;



	swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);

	swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));



	/* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */

	swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);

	IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);

	IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);

	IXGBE_WRITE_FLUSH(hw);

}
@@ -1454,15 +1459,15 @@ static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 
{

	u32 eec;



	eec = IXGBE_READ_REG(hw, IXGBE_EEC);

	eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));



	/* Toggle CS to flush commands */

	eec |= IXGBE_EEC_CS;

	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);

	IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);

	IXGBE_WRITE_FLUSH(hw);

	udelay(1);

	eec &= ~IXGBE_EEC_CS;

	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);

	IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);

	IXGBE_WRITE_FLUSH(hw);

	udelay(1);

}
@@ -1480,7 +1485,7 @@ static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 
	u32 mask;

	u32 i;



	eec = IXGBE_READ_REG(hw, IXGBE_EEC);

	eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));



	/*

	 * Mask is used to shift "count" bits of "data" out to the EEPROM
@@ -1501,7 +1506,7 @@ static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 
		else

			eec &= ~IXGBE_EEC_DI;



		IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);

		IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);

		IXGBE_WRITE_FLUSH(hw);



		udelay(1);
@@ -1518,7 +1523,7 @@ static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 


	/* We leave the "DI" bit set to "0" when we leave this routine. */

	eec &= ~IXGBE_EEC_DI;

	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);

	IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);

	IXGBE_WRITE_FLUSH(hw);

}
@@ -1539,7 +1544,7 @@ static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 
	 * the value of the "DO" bit.  During this "shifting in" process the

	 * "DI" bit should always be clear.

	 */

	eec = IXGBE_READ_REG(hw, IXGBE_EEC);

	eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));



	eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
@@ -1547,7 +1552,7 @@ static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 
		data = data << 1;

		ixgbe_raise_eeprom_clk(hw, &eec);



		eec = IXGBE_READ_REG(hw, IXGBE_EEC);

		eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));



		eec &= ~(IXGBE_EEC_DI);

		if (eec & IXGBE_EEC_DO)
@@ -1571,7 +1576,7 @@ static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 
	 * (setting the SK bit), then delay

	 */

	*eec = *eec | IXGBE_EEC_SK;

	IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);

	IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);

	IXGBE_WRITE_FLUSH(hw);

	udelay(1);

}
@@ -1588,7 +1593,7 @@ static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 
	 * delay

	 */

	*eec = *eec & ~IXGBE_EEC_SK;

	IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);

	IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);

	IXGBE_WRITE_FLUSH(hw);

	udelay(1);

}
@@ -1601,19 +1606,19 @@ static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 
{

	u32 eec;



	eec = IXGBE_READ_REG(hw, IXGBE_EEC);

	eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));



	eec |= IXGBE_EEC_CS;  /* Pull CS high */

	eec &= ~IXGBE_EEC_SK; /* Lower SCK */



	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);

	IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);

	IXGBE_WRITE_FLUSH(hw);



	udelay(1);



	/* Stop requesting EEPROM access */

	eec &= ~IXGBE_EEC_REQ;

	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);

	IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);



	hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);

drivers/net/ethernet/intel/ixgbe/ixgbe_common.h

+2 −0
Original line number Diff line number Diff line
@@ -118,6 +118,8 @@ bool ixgbe_mng_enabled(struct ixgbe_hw *hw); 
void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb,

			     u32 headroom, int strategy);



extern const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT];



#define IXGBE_I2C_THERMAL_SENSOR_ADDR	0xF8

#define IXGBE_EMC_INTERNAL_DATA		0x00

#define IXGBE_EMC_INTERNAL_THERM_LIMIT	0x20

drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c

+3 −3
Original line number Diff line number Diff line
@@ -470,16 +470,16 @@ static void ixgbe_get_regs(struct net_device *netdev, 
	regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);



	/* NVM Register */

	regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);

	regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw));

	regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);

	regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);

	regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw));

	regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);

	regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);

	regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);

	regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);

	regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);

	regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);

	regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);

	regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw));



	/* Interrupt */

	/* don't read EICR because it can clear interrupt causes, instead