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Commit 9a7ed8b8 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 5.2-rc6 into android-mainline



Linux 5.2-rc6

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
parents 29cf12fe 4b972a01
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+2 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ Greg Kroah-Hartman <greg@echidna.(none)>
Greg Kroah-Hartman <gregkh@suse.de>
Greg Kroah-Hartman <greg@kroah.com>
Gregory CLEMENT <gregory.clement@bootlin.com> <gregory.clement@free-electrons.com>
Hanjun Guo <guohanjun@huawei.com> <hanjun.guo@linaro.org>
Henk Vergonet <Henk.Vergonet@gmail.com>
Henrik Kretzschmar <henne@nachtwindheim.de>
Henrik Rydberg <rydberg@bitmath.org>
@@ -238,6 +239,7 @@ Vlad Dogaru <ddvlad@gmail.com> <vlad.dogaru@intel.com>
Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@virtuozzo.com>
Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@parallels.com>
Takashi YOSHII <takashi.yoshii.zj@renesas.com>
Will Deacon <will@kernel.org> <will.deacon@arm.com>
Yakir Yang <kuankuan.y@gmail.com> <ykk@rock-chips.com>
Yusuke Goda <goda.yusuke@renesas.com>
Gustavo Padovan <gustavo@las.ic.unicamp.br>
+11 −11
Original line number Diff line number Diff line
What:		/sys/bus/siox/devices/siox-X/active
KernelVersion:	4.16
Contact:	Gavin Schenk <g.schenk@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Contact:	Thorsten Scherer <t.scherer@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Description:
		On reading represents the current state of the bus. If it
		contains a "0" the bus is stopped and connected devices are
@@ -12,7 +12,7 @@ Description:

What:		/sys/bus/siox/devices/siox-X/device_add
KernelVersion:	4.16
Contact:	Gavin Schenk <g.schenk@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Contact:	Thorsten Scherer <t.scherer@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Description:
		Write-only file. Write

@@ -27,13 +27,13 @@ Description:

What:		/sys/bus/siox/devices/siox-X/device_remove
KernelVersion:	4.16
Contact:	Gavin Schenk <g.schenk@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Contact:	Thorsten Scherer <t.scherer@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Description:
		Write-only file. A single write removes the last device in the siox chain.

What:		/sys/bus/siox/devices/siox-X/poll_interval_ns
KernelVersion:	4.16
Contact:	Gavin Schenk <g.schenk@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Contact:	Thorsten Scherer <t.scherer@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Description:
		Defines the interval between two poll cycles in nano seconds.
		Note this is rounded to jiffies on writing. On reading the current value
@@ -41,33 +41,33 @@ Description:

What:		/sys/bus/siox/devices/siox-X-Y/connected
KernelVersion:	4.16
Contact:	Gavin Schenk <g.schenk@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Contact:	Thorsten Scherer <t.scherer@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Description:
		Read-only value. "0" means the Yth device on siox bus X isn't "connected" i.e.
		communication with it is not ensured. "1" signals a working connection.

What:		/sys/bus/siox/devices/siox-X-Y/inbytes
KernelVersion:	4.16
Contact:	Gavin Schenk <g.schenk@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Contact:	Thorsten Scherer <t.scherer@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Description:
		Read-only value reporting the inbytes value provided to siox-X/device_add

What:		/sys/bus/siox/devices/siox-X-Y/status_errors
KernelVersion:	4.16
Contact:	Gavin Schenk <g.schenk@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Contact:	Thorsten Scherer <t.scherer@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Description:
		Counts the number of time intervals when the read status byte doesn't yield the
		expected value.

What:		/sys/bus/siox/devices/siox-X-Y/type
KernelVersion:	4.16
Contact:	Gavin Schenk <g.schenk@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Contact:	Thorsten Scherer <t.scherer@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Description:
		Read-only value reporting the type value provided to siox-X/device_add.

What:		/sys/bus/siox/devices/siox-X-Y/watchdog
KernelVersion:	4.16
Contact:	Gavin Schenk <g.schenk@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Contact:	Thorsten Scherer <t.scherer@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Description:
		Read-only value reporting if the watchdog of the siox device is
		active. "0" means the watchdog is not active and the device is expected to
@@ -75,13 +75,13 @@ Description:

What:		/sys/bus/siox/devices/siox-X-Y/watchdog_errors
KernelVersion:	4.16
Contact:	Gavin Schenk <g.schenk@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Contact:	Thorsten Scherer <t.scherer@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Description:
		Read-only value reporting the number to time intervals when the
		watchdog was active.

What:		/sys/bus/siox/devices/siox-X-Y/outbytes
KernelVersion:	4.16
Contact:	Gavin Schenk <g.schenk@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Contact:	Thorsten Scherer <t.scherer@eckelmann.de>, Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Description:
		Read-only value reporting the outbytes value provided to siox-X/device_add.
+2 −2
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ Contact: Bjørn Mork <bjorn@mork.no>
Description:
		Unsigned integer.

		Write a number ranging from 1 to 127 to add a qmap mux
		Write a number ranging from 1 to 254 to add a qmap mux
		based network device, supported by recent Qualcomm based
		modems.

@@ -46,5 +46,5 @@ Contact: Bjørn Mork <bjorn@mork.no>
Description:
		Unsigned integer.

		Write a number ranging from 1 to 127 to delete a previously
		Write a number ranging from 1 to 254 to delete a previously
		created qmap mux based network device.
+1 −0
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@@ -4,6 +4,7 @@ Required properties:
 - compatible: Should be one of the following:
   - "microchip,mcp2510" for MCP2510.
   - "microchip,mcp2515" for MCP2515.
   - "microchip,mcp25625" for MCP25625.
 - reg: SPI chip select.
 - clocks: The clock feeding the CAN controller.
 - interrupts: Should contain IRQ line for the CAN controller.
+168 −0
Original line number Diff line number Diff line
# SPDX-License-Identifier: (GPL-2.0 OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/cpus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RISC-V bindings for 'cpus' DT nodes

maintainers:
  - Paul Walmsley <paul.walmsley@sifive.com>
  - Palmer Dabbelt <palmer@sifive.com>

allOf:
  - $ref: /schemas/cpus.yaml#

properties:
  $nodename:
    const: cpus
    description: Container of cpu nodes

  '#address-cells':
    const: 1
    description: |
      A single unsigned 32-bit integer uniquely identifies each RISC-V
      hart in a system.  (See the "reg" node under the "cpu" node,
      below).

  '#size-cells':
    const: 0

patternProperties:
  '^cpu@[0-9a-f]+$':
    properties:
      compatible:
        type: array
        items:
          - enum:
              - sifive,rocket0
              - sifive,e5
              - sifive,e51
              - sifive,u54-mc
              - sifive,u54
              - sifive,u5
          - const: riscv
        description:
          Identifies that the hart uses the RISC-V instruction set
          and identifies the type of the hart.

      mmu-type:
        allOf:
          - $ref: "/schemas/types.yaml#/definitions/string"
          - enum:
              - riscv,sv32
              - riscv,sv39
              - riscv,sv48
        description:
          Identifies the MMU address translation mode used on this
          hart.  These values originate from the RISC-V Privileged
          Specification document, available from
          https://riscv.org/specifications/

      riscv,isa:
        allOf:
          - $ref: "/schemas/types.yaml#/definitions/string"
          - enum:
              - rv64imac
              - rv64imafdc
        description:
          Identifies the specific RISC-V instruction set architecture
          supported by the hart.  These are documented in the RISC-V
          User-Level ISA document, available from
          https://riscv.org/specifications/

      timebase-frequency:
        type: integer
        minimum: 1
        description:
          Specifies the clock frequency of the system timer in Hz.
          This value is common to all harts on a single system image.

      interrupt-controller:
        type: object
        description: Describes the CPU's local interrupt controller

        properties:
          '#interrupt-cells':
            const: 1

          compatible:
            const: riscv,cpu-intc

          interrupt-controller: true

        required:
          - '#interrupt-cells'
          - compatible
          - interrupt-controller

    required:
      - riscv,isa
      - timebase-frequency
      - interrupt-controller

examples:
  - |
    // Example 1: SiFive Freedom U540G Development Kit
    cpus {
        #address-cells = <1>;
        #size-cells = <0>;
        timebase-frequency = <1000000>;
        cpu@0 {
                clock-frequency = <0>;
                compatible = "sifive,rocket0", "riscv";
                device_type = "cpu";
                i-cache-block-size = <64>;
                i-cache-sets = <128>;
                i-cache-size = <16384>;
                reg = <0>;
                riscv,isa = "rv64imac";
                cpu_intc0: interrupt-controller {
                        #interrupt-cells = <1>;
                        compatible = "riscv,cpu-intc";
                        interrupt-controller;
                };
        };
        cpu@1 {
                clock-frequency = <0>;
                compatible = "sifive,rocket0", "riscv";
                d-cache-block-size = <64>;
                d-cache-sets = <64>;
                d-cache-size = <32768>;
                d-tlb-sets = <1>;
                d-tlb-size = <32>;
                device_type = "cpu";
                i-cache-block-size = <64>;
                i-cache-sets = <64>;
                i-cache-size = <32768>;
                i-tlb-sets = <1>;
                i-tlb-size = <32>;
                mmu-type = "riscv,sv39";
                reg = <1>;
                riscv,isa = "rv64imafdc";
                tlb-split;
                cpu_intc1: interrupt-controller {
                        #interrupt-cells = <1>;
                        compatible = "riscv,cpu-intc";
                        interrupt-controller;
                };
        };
    };

  - |
    // Example 2: Spike ISA Simulator with 1 Hart
    cpus {
            cpu@0 {
                    device_type = "cpu";
                    reg = <0>;
                    compatible = "riscv";
                    riscv,isa = "rv64imafdc";
                    mmu-type = "riscv,sv48";
                    interrupt-controller {
                            #interrupt-cells = <1>;
                            interrupt-controller;
                            compatible = "riscv,cpu-intc";
                    };
            };
    };
...
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