Loading display/yupik-sde-common.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -10,8 +10,8 @@ "vbif_phys", "regdma_phys"; clock-rate = <0 0 0 0 506666667 19200000 506666667 19200000>; clock-max-rate = <0 0 0 0 608000000 19200000 608000000 clock-rate = <0 0 0 506666667 19200000 506666667 19200000>; clock-max-rate = <0 0 0 608000000 19200000 608000000 608000000>; /* interrupt config */ Loading display/yupik-sde.dtsi +1 −2 Original line number Diff line number Diff line Loading @@ -163,7 +163,6 @@ &mdss_mdp { clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, <&gcc GCC_DISP_SF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, Loading @@ -171,7 +170,7 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc DISP_CC_MDSS_ROT_CLK>; clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", clock-names = "gcc_bus", "gcc_nrt_bus", "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; Loading Loading
display/yupik-sde-common.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -10,8 +10,8 @@ "vbif_phys", "regdma_phys"; clock-rate = <0 0 0 0 506666667 19200000 506666667 19200000>; clock-max-rate = <0 0 0 0 608000000 19200000 608000000 clock-rate = <0 0 0 506666667 19200000 506666667 19200000>; clock-max-rate = <0 0 0 608000000 19200000 608000000 608000000>; /* interrupt config */ Loading
display/yupik-sde.dtsi +1 −2 Original line number Diff line number Diff line Loading @@ -163,7 +163,6 @@ &mdss_mdp { clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, <&gcc GCC_DISP_SF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, Loading @@ -171,7 +170,7 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc DISP_CC_MDSS_ROT_CLK>; clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", clock-names = "gcc_bus", "gcc_nrt_bus", "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; Loading