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Commit 99d10c01 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add support for RPMHCC for YUPIK"

parents 1f6d511b b04ca6dd

bindings/clock/qcom,rpmh-clk.txt

+1 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ Required properties : 
		"qcom,sdm845-rpmh-clk"

		"qcom,sm8150-rpmh-clk"

		"qcom,sdxlemur-rpmh-clk"

		"qcom,yupik-rpmh-clk"



- #clock-cells : must contain 1

qcom/yupik-rumi.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -28,6 +28,21 @@ 
				     0x0 0x4>;

	};



	bi_tcxo: bi_tcxo {

		compatible = "fixed-factor-clock";

		clock-mult = <1>;

		clock-div = <4>;

		clocks = <&xo_board>;

		#clock-cells = <0>;

	};



	bi_tcxo_ao: bi_tcxo_ao {

		compatible = "fixed-factor-clock";

		clock-mult = <1>;

		clock-div = <4>;

		clocks = <&xo_board>;

		#clock-cells = <0>;

	};

};



&usb0 {
@@ -78,6 +93,11 @@ 
	qcom,rumi_platform;

};



&rpmhcc {

	compatible = "qcom,dummycc";

	clock-output-names = "rpmhcc_clocks";

};



&gcc {

	clocks = <&bi_tcxo>, <&sleep_clk>;

};

qcom/yupik.dtsi

+6 −23
Original line number Diff line number Diff line
@@ -569,22 +569,6 @@ 
		};

	};



	bi_tcxo: bi_tcxo {

		compatible = "fixed-factor-clock";

		clock-mult = <1>;

		clock-div = <4>;

		clocks = <&xo_board>;

		#clock-cells = <0>;

	};



	bi_tcxo_ao: bi_tcxo_ao {

		compatible = "fixed-factor-clock";

		clock-mult = <1>;

		clock-div = <4>;

		clocks = <&xo_board>;

		#clock-cells = <0>;

	};



	aopcc: qcom,aopcc {

		compatible = "qcom,dummycc";

		clock-output-names = "aopcc_clocks";
@@ -592,13 +576,6 @@ 
		#reset-cells = <1>;

	};



	rpmhcc: qcom,rpmhcc {

		compatible = "qcom,dummycc";

		clock-output-names = "rpmhcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	gcc: clock-controller@100000 {

		compatible = "qcom,yupik-gcc", "syscon";

		reg = <0x100000 0x1f0000>;
@@ -918,6 +895,12 @@ 
		system_pm {

			compatible = "qcom,system-pm";

		};



		rpmhcc: qcom,rpmhclk {

			compatible = "qcom,yupik-rpmh-clk";

			#clock-cells = <1>;

		};



	};



	disp_rsc: rsc@af20000 {