Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9975a5f2 authored by Borislav Petkov's avatar Borislav Petkov
Browse files

amd64_edac: Fix DCT base address selector 



The correct check is to verify whether in high range we're below 4GB
and not to extract the DctSelBaseAddr again. See "2.8.5 Routing DRAM
Requests" in the F10h BKDG.

Cc: <stable@kernel.org> # .32.x .33.x .34.x
Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
Acked-by: default avatarDoug Thompson <dougthompson@xmission.com>
parent f4347553

drivers/edac/amd64_edac.c

+1 −1
Original line number Diff line number Diff line
@@ -1435,7 +1435,7 @@ static inline u64 f10_get_base_addr_offset(u64 sys_addr, int hi_range_sel, 
	u64 chan_off;



	if (hi_range_sel) {

		if (!(dct_sel_base_addr & 0xFFFFF800) &&

		if (!(dct_sel_base_addr & 0xFFFF0000) &&

		   hole_valid && (sys_addr >= 0x100000000ULL))

			chan_off = hole_off << 16;

		else