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Commit 991117ee authored by Christian Hewitt's avatar Christian Hewitt Committed by Greg Kroah-Hartman
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drm/meson: fix colour distortion from HDR set during vendor u-boot 

[ Upstream commit bf33677a3c394bb8fddd48d3bbc97adf0262e045 ]

Add support for the OSD1 HDR registers so meson DRM can handle the HDR
properties set by Amlogic u-boot on G12A and newer devices which result
in blue/green/pink colour distortion to display output.

This takes the original patch submissions from Mathias [0] and [1] with
corrections for formatting and the missing description and attribution
needed for merge.

[0] https://lore.kernel.org/linux-amlogic/59dfd7e6-fc91-3d61-04c4-94e078a3188c@baylibre.com/T/
[1] https://lore.kernel.org/linux-amlogic/CAOKfEHBx_fboUqkENEMd-OC-NSrf46nto+vDLgvgttzPe99kXg@mail.gmail.com/T/#u



Fixes: 72888394 ("drm/meson: Add G12A Support for VIU setup")
Suggested-by: default avatarMathias Steiger <mathias.steiger@googlemail.com>
Signed-off-by: default avatarChristian Hewitt <christianshewitt@gmail.com>
Tested-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Tested-by: default avatarPhilip Milev <milev.philip@gmail.com>
[narmsrong: adding missing space on second tested-by tag]
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210806094005.7136-1-christianshewitt@gmail.com


Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent e114f15d

drivers/gpu/drm/meson/meson_registers.h

+5 −0
Original line number Diff line number Diff line
@@ -590,6 +590,11 @@ 
#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 0x3dbc

#define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd



/* osd1 HDR */

#define OSD1_HDR2_CTRL 0x38a0

#define OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN       BIT(13)

#define OSD1_HDR2_CTRL_REG_ONLY_MAT            BIT(16)



/* osd2 scaler */

#define OSD2_VSC_PHASE_STEP 0x3d00

#define OSD2_VSC_INI_PHASE 0x3d01

drivers/gpu/drm/meson/meson_viu.c

+6 −1
Original line number Diff line number Diff line
@@ -356,9 +356,14 @@ void meson_viu_init(struct meson_drm *priv) 
	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||

	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))

		meson_viu_load_matrix(priv);

	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))

	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {

		meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff,

					       true);

		/* fix green/pink color distortion from vendor u-boot */

		writel_bits_relaxed(OSD1_HDR2_CTRL_REG_ONLY_MAT |

				OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN, 0,

				priv->io_base + _REG(OSD1_HDR2_CTRL));

	}



	/* Initialize OSD1 fifo control register */

	reg = VIU_OSD_DDR_PRIORITY_URGENT |