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Commit 98d8a60e authored Jun 29, 2015 by Stephen Boyd Committed by Michael Turquette Aug 24, 2015

clk: Convert __clk_get_flags() to clk_hw_get_flags()



Mostly converted with the following snippet:

@@
struct clk_hw *E;
@@

-__clk_get_flags(E->clk)
+clk_hw_get_flags(E)

Acked-by: Tero Kristo <t-kristo@ti.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

parent 497295af

drivers/clk/clk-cdce706.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -310,7 +310,7 @@ static long cdce706_divider_round_rate(struct clk_hw *hw, unsigned long rate,
	if (!mul)		if (!mul)
	div = CDCE706_DIVIDER_DIVIDER_MAX;		div = CDCE706_DIVIDER_DIVIDER_MAX;

	if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {		if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
	unsigned long best_diff = rate;		unsigned long best_diff = rate;
	unsigned long best_div = 0;		unsigned long best_div = 0;
	struct clk *gp_clk = cdce->clkin_clk[cdce->clkin[0].parent];		struct clk *gp_clk = cdce->clkin_clk[cdce->clkin[0].parent];

drivers/clk/clk-composite.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -78,7 +78,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw,
	mux_hw && mux_ops && mux_ops->set_parent) {		mux_hw && mux_ops && mux_ops->set_parent) {
	req->best_parent_hw = NULL;		req->best_parent_hw = NULL;

	if (__clk_get_flags(hw->clk) & CLK_SET_RATE_NO_REPARENT) {		if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
	parent = clk_get_parent(mux_hw->clk);		parent = clk_get_parent(mux_hw->clk);
	req->best_parent_hw = __clk_get_hw(parent);		req->best_parent_hw = __clk_get_hw(parent);
	req->best_parent_rate = __clk_get_rate(parent);		req->best_parent_rate = __clk_get_rate(parent);

drivers/clk/clk-divider.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -290,7 +290,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,

	maxdiv = _get_maxdiv(table, width, flags);		maxdiv = _get_maxdiv(table, width, flags);

	if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {		if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
	parent_rate = *best_parent_rate;		parent_rate = *best_parent_rate;
	bestdiv = _div_round(table, parent_rate, rate, flags);		bestdiv = _div_round(table, parent_rate, rate, flags);
	bestdiv = bestdiv == 0 ? 1 : bestdiv;		bestdiv = bestdiv == 0 ? 1 : bestdiv;

drivers/clk/clk-fixed-factor.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -41,7 +41,7 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
	{		{
	struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);		struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);

	if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {		if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
	unsigned long best_parent;		unsigned long best_parent;

	best_parent = (rate / fix->mult) * fix->div;		best_parent = (rate / fix->mult) * fix->div;

drivers/clk/clk-si5351.c

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -663,7 +663,7 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
	divby4 = 1;		divby4 = 1;

	/* multisync can set pll */		/* multisync can set pll */
	if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) {		if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
	/*		/*
	* find largest integer divider for max		* find largest integer divider for max
	* vco frequency and given target rate		* vco frequency and given target rate
	@@ -1013,7 +1013,7 @@ static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
	rate = SI5351_CLKOUT_MIN_FREQ;		rate = SI5351_CLKOUT_MIN_FREQ;

	/* request frequency if multisync master */		/* request frequency if multisync master */
	if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) {		if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
	/* use r divider for frequencies below 1MHz */		/* use r divider for frequencies below 1MHz */
	rdiv = SI5351_OUTPUT_CLK_DIV_1;		rdiv = SI5351_OUTPUT_CLK_DIV_1;
	while (rate < SI5351_MULTISYNTH_MIN_FREQ &&		while (rate < SI5351_MULTISYNTH_MIN_FREQ &&