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Commit 98b28f93 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add eMMC, SD card support for holi"

parents e77c4849 248a81ad

qcom/holi-pinctrl.dtsi

+102 −0
Original line number Diff line number Diff line
@@ -384,6 +384,108 @@ 
			};

		};



		sdc1_on: sdc1_on {

			clk {

				pins = "sdc1_clk";

				bias-disable;

				drive-strength = <16>;

			};



			cmd {

				pins = "sdc1_cmd";

				bias-pull-up;

				drive-strength = <10>;

			};



			data {

				pins = "sdc1_data";

				bias-pull-up;

				drive-strength = <10>;

			};



			rclk {

				pins = "sdc1_rclk";

				bias-pull-down;

			};

		};



		sdc1_off: sdc1_off {

			clk {

				pins = "sdc1_clk";

				bias-disable;

				drive-strength = <2>;

			};



			cmd {

				pins = "sdc1_cmd";

				bias-pull-up;

				drive-strength = <2>;

			};



			data {

				pins = "sdc1_data";

				bias-pull-up;

				drive-strength = <2>;

			};



			rclk {

				pins = "sdc1_rclk";

				bias-pull-down;

			};

		};



		sdc2_on: sdc2_on {

			clk {

				pins = "sdc2_clk";

				bias-disable;

				drive-strength = <16>;

			};



			cmd {

				pins = "sdc2_cmd";

				bias-pull-up;

				drive-strength = <10>;

			};



			data {

				pins = "sdc2_data";

				bias-pull-up;

				drive-strength = <10>;

			};



			sd-cd {

				pins = "gpio94";

				bias-pull-up;

				drive-strength = <2>;

			};

		};



		sdc2_off: sdc2_off {

			clk {

				pins = "sdc2_clk";

				bias-disable;

				drive-strength = <2>;

			};



			cmd {

				pins = "sdc2_cmd";

				bias-pull-up;

				drive-strength = <2>;

			};



			data {

				pins = "sdc2_data";

				bias-pull-up;

				drive-strength = <2>;

			};



			sd-cd {

				pins = "gpio94";

				bias-disable;

				drive-strength = <2>;

			};

		};



		pmx_sde_te: pmx_sde_te {

			sde_te_active: sde_te_active {

				mux {

qcom/holi-rumi.dtsi

+41 −0
Original line number Diff line number Diff line 
#include <dt-bindings/gpio/gpio.h>

&soc {

	timer {

		clock-frequency = <500000>;
@@ -43,6 +44,46 @@ 
	};

};



&sdhc_1 {

	status = "ok";



	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&sdc1_on>;

	pinctrl-1 = <&sdc1_off>;



	cap-mmc-highspeed;



	vdd-supply = <&L7E>;

	qcom,vdd-voltage-level = <2960000 2960000>;

	qcom,vdd-current-level = <0 570000>;



	vdd-io-supply = <&L12A>;

	qcom,vdd-io-always-on;

	qcom,vdd-io-lpm-sup;

	qcom,vdd-io-voltage-level = <1800000 1800000>;

	qcom,vdd-io-current-level = <0 325000>;

};



&sdhc_2 {

	status = "ok";



	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&sdc2_on>;

	pinctrl-1 = <&sdc2_off>;



	cap-sd-highspeed;



	vdd-supply = <&L9E>;

	qcom,vdd-voltage-level = <2960000 2960000>;

	qcom,vdd-current-level = <0 800000>;



	vdd-io-supply = <&L6E>;

	qcom,vdd-io-voltage-level = <2960000 2960000>;

	qcom,vdd-io-current-level = <0 22000>;



	cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;

};



&ufsphy_mem {

		compatible = "qcom,ufs-phy-qrbtc-sdm845";

qcom/holi.dtsi

+45 −0
Original line number Diff line number Diff line
@@ -22,6 +22,9 @@ 


	aliases {

		ufshc1 = &ufshc_mem; /* Embedded  UFS Slot */



		sdhc1 = &sdhc_1; /*SDC1 eMMC slot*/

		sdhc2 = &sdhc_2; /* SDC2 SD card slot */

		serial0 = &qupv3_se9_2uart;

		hsuart0 = &qupv3_se1_4uart;

	};
@@ -1517,6 +1520,48 @@ 
		status = "disabled";

	};



	sdhc_1: sdhci@4744000 {

		compatible = "qcom,sdhci-msm-v5";

		reg = <0x04744000 0x1000>, <0x04745000 0x1000>;

		reg-names = "hc_mem", "cqhci_mem";



		iommus = <&apps_smmu 0x20 0x0>;

		qcom,iommu-dma = "bypass";



		interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "hc_irq", "pwr_irq";



		clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;

		clock-names = "core", "iface";



		bus-width = <8>;

		non-removable;

		supports-cqe;



		status = "disabled";

	};



	sdhc_2: sdhci@4784000 {

		compatible = "qcom,sdhci-msm-v5";

		reg = <0x04784000 0x1000>;

		reg-names = "hc_mem";



		interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "hc_irq", "pwr_irq";



		clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;

		clock-names = "core", "iface";



		bus-width = <4>;



		iommus = <&apps_smmu 0x40 0x0>;

		qcom,iommu-dma = "bypass";



		status = "disabled";

	};



	qcom,lpass@a400000 {

		compatible = "qcom,pil-tz-generic";

		reg = <0xa400000 0x00100>;