Loading Documentation/devicetree/bindings/dma/dma.txt +4 −0 Original line number Diff line number Diff line Loading @@ -16,6 +16,9 @@ Optional properties: - dma-channels: Number of DMA channels supported by the controller. - dma-requests: Number of DMA request signals supported by the controller. - dma-channel-mask: Bitmask of available DMA channels in ascending order that are not reserved by firmware and are available to the kernel. i.e. first channel corresponds to LSB. Example: Loading @@ -29,6 +32,7 @@ Example: #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; dma-channel-mask = <0xfffe> }; * DMA router Loading Documentation/devicetree/bindings/dma/k3dma.txt +3 −1 Original line number Diff line number Diff line Loading @@ -3,7 +3,9 @@ See dma.txt first Required properties: - compatible: Should be "hisilicon,k3-dma-1.0" - compatible: Must be one of - "hisilicon,k3-dma-1.0" - "hisilicon,hisi-pcm-asp-dma-1.0" - reg: Should contain DMA registers location and length. - interrupts: Should contain one interrupt shared by all channel - #dma-cells: see dma.txt, should be 1, para number Loading drivers/dma/k3dma.c +52 −9 Original line number Diff line number Diff line Loading @@ -52,8 +52,6 @@ #define CX_SRC 0x814 #define CX_DST 0x818 #define CX_CFG 0x81c #define AXI_CFG 0x820 #define AXI_CFG_DEFAULT 0x201201 #define CX_LLI_CHAIN_EN 0x2 #define CX_CFG_EN 0x1 Loading Loading @@ -113,9 +111,18 @@ struct k3_dma_dev { struct dma_pool *pool; u32 dma_channels; u32 dma_requests; u32 dma_channel_mask; unsigned int irq; }; #define K3_FLAG_NOCLK BIT(1) struct k3dma_soc_data { unsigned long flags; }; #define to_k3_dma(dmadev) container_of(dmadev, struct k3_dma_dev, slave) static int k3_dma_config_write(struct dma_chan *chan, Loading Loading @@ -161,7 +168,6 @@ static void k3_dma_set_desc(struct k3_dma_phy *phy, struct k3_desc_hw *hw) writel_relaxed(hw->count, phy->base + CX_CNT0); writel_relaxed(hw->saddr, phy->base + CX_SRC); writel_relaxed(hw->daddr, phy->base + CX_DST); writel_relaxed(AXI_CFG_DEFAULT, phy->base + AXI_CFG); writel_relaxed(hw->config, phy->base + CX_CFG); } Loading Loading @@ -314,6 +320,9 @@ static void k3_dma_tasklet(unsigned long arg) /* check new channel request in d->chan_pending */ spin_lock_irq(&d->lock); for (pch = 0; pch < d->dma_channels; pch++) { if (!(d->dma_channel_mask & (1 << pch))) continue; p = &d->phy[pch]; if (p->vchan == NULL && !list_empty(&d->chan_pending)) { Loading @@ -331,6 +340,9 @@ static void k3_dma_tasklet(unsigned long arg) spin_unlock_irq(&d->lock); for (pch = 0; pch < d->dma_channels; pch++) { if (!(d->dma_channel_mask & (1 << pch))) continue; if (pch_alloc & (1 << pch)) { p = &d->phy[pch]; c = p->vchan; Loading Loading @@ -790,8 +802,21 @@ static int k3_dma_transfer_resume(struct dma_chan *chan) return 0; } static const struct k3dma_soc_data k3_v1_dma_data = { .flags = 0, }; static const struct k3dma_soc_data asp_v1_dma_data = { .flags = K3_FLAG_NOCLK, }; static const struct of_device_id k3_pdma_dt_ids[] = { { .compatible = "hisilicon,k3-dma-1.0", }, { .compatible = "hisilicon,k3-dma-1.0", .data = &k3_v1_dma_data }, { .compatible = "hisilicon,hisi-pcm-asp-dma-1.0", .data = &asp_v1_dma_data }, {} }; MODULE_DEVICE_TABLE(of, k3_pdma_dt_ids); Loading @@ -810,6 +835,7 @@ static struct dma_chan *k3_of_dma_simple_xlate(struct of_phandle_args *dma_spec, static int k3_dma_probe(struct platform_device *op) { const struct k3dma_soc_data *soc_data; struct k3_dma_dev *d; const struct of_device_id *of_id; struct resource *iores; Loading @@ -823,6 +849,10 @@ static int k3_dma_probe(struct platform_device *op) if (!d) return -ENOMEM; soc_data = device_get_match_data(&op->dev); if (!soc_data) return -EINVAL; d->base = devm_ioremap_resource(&op->dev, iores); if (IS_ERR(d->base)) return PTR_ERR(d->base); Loading @@ -833,13 +863,22 @@ static int k3_dma_probe(struct platform_device *op) "dma-channels", &d->dma_channels); of_property_read_u32((&op->dev)->of_node, "dma-requests", &d->dma_requests); ret = of_property_read_u32((&op->dev)->of_node, "dma-channel-mask", &d->dma_channel_mask); if (ret) { dev_warn(&op->dev, "dma-channel-mask doesn't exist, considering all as available.\n"); d->dma_channel_mask = (u32)~0UL; } } if (!(soc_data->flags & K3_FLAG_NOCLK)) { d->clk = devm_clk_get(&op->dev, NULL); if (IS_ERR(d->clk)) { dev_err(&op->dev, "no dma clk\n"); return PTR_ERR(d->clk); } } irq = platform_get_irq(op, 0); ret = devm_request_irq(&op->dev, irq, Loading @@ -862,8 +901,12 @@ static int k3_dma_probe(struct platform_device *op) return -ENOMEM; for (i = 0; i < d->dma_channels; i++) { struct k3_dma_phy *p = &d->phy[i]; struct k3_dma_phy *p; if (!(d->dma_channel_mask & BIT(i))) continue; p = &d->phy[i]; p->idx = i; p->base = d->base + i * 0x40; } Loading Loading
Documentation/devicetree/bindings/dma/dma.txt +4 −0 Original line number Diff line number Diff line Loading @@ -16,6 +16,9 @@ Optional properties: - dma-channels: Number of DMA channels supported by the controller. - dma-requests: Number of DMA request signals supported by the controller. - dma-channel-mask: Bitmask of available DMA channels in ascending order that are not reserved by firmware and are available to the kernel. i.e. first channel corresponds to LSB. Example: Loading @@ -29,6 +32,7 @@ Example: #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; dma-channel-mask = <0xfffe> }; * DMA router Loading
Documentation/devicetree/bindings/dma/k3dma.txt +3 −1 Original line number Diff line number Diff line Loading @@ -3,7 +3,9 @@ See dma.txt first Required properties: - compatible: Should be "hisilicon,k3-dma-1.0" - compatible: Must be one of - "hisilicon,k3-dma-1.0" - "hisilicon,hisi-pcm-asp-dma-1.0" - reg: Should contain DMA registers location and length. - interrupts: Should contain one interrupt shared by all channel - #dma-cells: see dma.txt, should be 1, para number Loading
drivers/dma/k3dma.c +52 −9 Original line number Diff line number Diff line Loading @@ -52,8 +52,6 @@ #define CX_SRC 0x814 #define CX_DST 0x818 #define CX_CFG 0x81c #define AXI_CFG 0x820 #define AXI_CFG_DEFAULT 0x201201 #define CX_LLI_CHAIN_EN 0x2 #define CX_CFG_EN 0x1 Loading Loading @@ -113,9 +111,18 @@ struct k3_dma_dev { struct dma_pool *pool; u32 dma_channels; u32 dma_requests; u32 dma_channel_mask; unsigned int irq; }; #define K3_FLAG_NOCLK BIT(1) struct k3dma_soc_data { unsigned long flags; }; #define to_k3_dma(dmadev) container_of(dmadev, struct k3_dma_dev, slave) static int k3_dma_config_write(struct dma_chan *chan, Loading Loading @@ -161,7 +168,6 @@ static void k3_dma_set_desc(struct k3_dma_phy *phy, struct k3_desc_hw *hw) writel_relaxed(hw->count, phy->base + CX_CNT0); writel_relaxed(hw->saddr, phy->base + CX_SRC); writel_relaxed(hw->daddr, phy->base + CX_DST); writel_relaxed(AXI_CFG_DEFAULT, phy->base + AXI_CFG); writel_relaxed(hw->config, phy->base + CX_CFG); } Loading Loading @@ -314,6 +320,9 @@ static void k3_dma_tasklet(unsigned long arg) /* check new channel request in d->chan_pending */ spin_lock_irq(&d->lock); for (pch = 0; pch < d->dma_channels; pch++) { if (!(d->dma_channel_mask & (1 << pch))) continue; p = &d->phy[pch]; if (p->vchan == NULL && !list_empty(&d->chan_pending)) { Loading @@ -331,6 +340,9 @@ static void k3_dma_tasklet(unsigned long arg) spin_unlock_irq(&d->lock); for (pch = 0; pch < d->dma_channels; pch++) { if (!(d->dma_channel_mask & (1 << pch))) continue; if (pch_alloc & (1 << pch)) { p = &d->phy[pch]; c = p->vchan; Loading Loading @@ -790,8 +802,21 @@ static int k3_dma_transfer_resume(struct dma_chan *chan) return 0; } static const struct k3dma_soc_data k3_v1_dma_data = { .flags = 0, }; static const struct k3dma_soc_data asp_v1_dma_data = { .flags = K3_FLAG_NOCLK, }; static const struct of_device_id k3_pdma_dt_ids[] = { { .compatible = "hisilicon,k3-dma-1.0", }, { .compatible = "hisilicon,k3-dma-1.0", .data = &k3_v1_dma_data }, { .compatible = "hisilicon,hisi-pcm-asp-dma-1.0", .data = &asp_v1_dma_data }, {} }; MODULE_DEVICE_TABLE(of, k3_pdma_dt_ids); Loading @@ -810,6 +835,7 @@ static struct dma_chan *k3_of_dma_simple_xlate(struct of_phandle_args *dma_spec, static int k3_dma_probe(struct platform_device *op) { const struct k3dma_soc_data *soc_data; struct k3_dma_dev *d; const struct of_device_id *of_id; struct resource *iores; Loading @@ -823,6 +849,10 @@ static int k3_dma_probe(struct platform_device *op) if (!d) return -ENOMEM; soc_data = device_get_match_data(&op->dev); if (!soc_data) return -EINVAL; d->base = devm_ioremap_resource(&op->dev, iores); if (IS_ERR(d->base)) return PTR_ERR(d->base); Loading @@ -833,13 +863,22 @@ static int k3_dma_probe(struct platform_device *op) "dma-channels", &d->dma_channels); of_property_read_u32((&op->dev)->of_node, "dma-requests", &d->dma_requests); ret = of_property_read_u32((&op->dev)->of_node, "dma-channel-mask", &d->dma_channel_mask); if (ret) { dev_warn(&op->dev, "dma-channel-mask doesn't exist, considering all as available.\n"); d->dma_channel_mask = (u32)~0UL; } } if (!(soc_data->flags & K3_FLAG_NOCLK)) { d->clk = devm_clk_get(&op->dev, NULL); if (IS_ERR(d->clk)) { dev_err(&op->dev, "no dma clk\n"); return PTR_ERR(d->clk); } } irq = platform_get_irq(op, 0); ret = devm_request_irq(&op->dev, irq, Loading @@ -862,8 +901,12 @@ static int k3_dma_probe(struct platform_device *op) return -ENOMEM; for (i = 0; i < d->dma_channels; i++) { struct k3_dma_phy *p = &d->phy[i]; struct k3_dma_phy *p; if (!(d->dma_channel_mask & BIT(i))) continue; p = &d->phy[i]; p->idx = i; p->base = d->base + i * 0x40; } Loading